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authorPeter Griffin <peter.griffin@linaro.org>2024-04-26 13:20:02 +0100
committerMartin K. Petersen <martin.petersen@oracle.com>2024-05-06 21:34:37 -0400
commitc9deb9a4f574b49bfd00be88aba470659d2db671 (patch)
tree2b05749d75f0864130027a3df79fc1aa35c691e8 /drivers/ufs
parent9238cad67969e7001e296eaedcdffc63fc38ab30 (diff)
scsi: ufs: exynos: Allow max frequencies up to 267Mhz
Platforms such as Tensor gs101 the pclk frequency is 267Mhz. Increase PCLK_AVAIL_MAX so we don't fail the frequency check. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240426122004.2249178-5-peter.griffin@linaro.org Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/ufs')
-rw-r--r--drivers/ufs/host/ufs-exynos.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
index acf07cc54684..7acc13914100 100644
--- a/drivers/ufs/host/ufs-exynos.h
+++ b/drivers/ufs/host/ufs-exynos.h
@@ -116,7 +116,7 @@ struct exynos_ufs;
#define PA_HIBERN8TIME_VAL 0x20
#define PCLK_AVAIL_MIN 70000000
-#define PCLK_AVAIL_MAX 167000000
+#define PCLK_AVAIL_MAX 267000000
struct exynos_ufs_uic_attr {
/* TX Attributes */