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authorPeter Wang <peter.wang@mediatek.com>2022-06-23 11:50:47 +0800
committerMartin K. Petersen <martin.petersen@oracle.com>2022-06-27 23:17:36 -0400
commit2bae03a6ac985fe80a7a228af3bcc2d5dbe43381 (patch)
treef5432a979cf7a85fc6fa75cac3816d690f9a8d3d /drivers/ufs/host/ufs-mediatek.c
parent981b4ac04c2f7c24724d3b3a62c3d0c2fc9adcb7 (diff)
scsi: ufs: ufs-mediatek: Prevent host hang by setting CLK_CG early
Some UFSHCI hosts in MediaTek UFS platform need workaround to prevent host hang issue by setting CLK_CG bit before host is enabled. This operation shall have no side effect on those platforms which do not support this bit. Link: https://lore.kernel.org/r/20220623035052.18802-4-stanley.chu@mediatek.com Reviewed-by: Stanley Chu <stanley.chu@mediatek.com> Reviewed-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Peter Wang <peter.wang@mediatek.com> Signed-off-by: Stanley Chu <stanley.chu@mediatek.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/ufs/host/ufs-mediatek.c')
-rw-r--r--drivers/ufs/host/ufs-mediatek.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index b8f2a74d2a51..b15351c2235b 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -183,6 +183,14 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
hba->capabilities &= ~MASK_AUTO_HIBERN8_SUPPORT;
hba->ahit = 0;
}
+
+ /*
+ * Turn on CLK_CG early to bypass abnormal ERR_CHK signal
+ * to prevent host hang issue
+ */
+ ufshcd_writel(hba,
+ ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80,
+ REG_UFS_XOUFS_CTRL);
}
return 0;