diff options
| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2019-04-09 14:25:13 +0300 |
|---|---|---|
| committer | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2019-05-06 17:53:58 +0300 |
| commit | 9eac0d75f132608159eb649ceadfc4e53b2a1686 (patch) | |
| tree | f635cc2aea8ef7ac62ba7d000822acd1ac01275c /drivers/platform/x86 | |
| parent | 0084cf6a504347da07066e020d0cf7b87eb2a274 (diff) | |
platform/x86: intel_pmc_ipc: Apply same width for offset definitions
Apply same width for offset definitions to make code more consistent.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Diffstat (limited to 'drivers/platform/x86')
| -rw-r--r-- | drivers/platform/x86/intel_pmc_ipc.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c index eb0b342996ca..9007aa717586 100644 --- a/drivers/platform/x86/intel_pmc_ipc.c +++ b/drivers/platform/x86/intel_pmc_ipc.c @@ -40,7 +40,7 @@ * The ARC handles the interrupt and services it, writing optional data to * the IPC1 registers, updates the IPC_STS response register with the status. */ -#define IPC_CMD 0x0 +#define IPC_CMD 0x00 #define IPC_CMD_MSI BIT(8) #define IPC_CMD_SIZE 16 #define IPC_CMD_SUBCMD 12 @@ -101,8 +101,8 @@ #define TELEM_SSRAM_SIZE 240 #define TELEM_PMC_SSRAM_OFFSET 0x1B00 #define TELEM_PUNIT_SSRAM_OFFSET 0x1A00 -#define TCO_PMC_OFFSET 0x8 -#define TCO_PMC_SIZE 0x4 +#define TCO_PMC_OFFSET 0x08 +#define TCO_PMC_SIZE 0x04 /* PMC register bit definitions */ |