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authorYixun Lan <yixun.lan@amlogic.com>2018-05-09 22:08:27 +0000
committerLinus Walleij <linus.walleij@linaro.org>2018-05-16 16:23:57 +0200
commitc0136ef651e86a1a7aabe0e1735156526e5d3016 (patch)
treedc08e3361aefcbc16d70720ea85d1fbfc28631af /drivers/pinctrl
parente3678b64701e4aa48b1d91a494206dea9ec8bafa (diff)
pinctrl: nand: meson-gxl: fix missing data pins
The data pin 0-7 of the NAND controller are actually missing from the nand pinctrl group, so we fix it here. Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions") Reported-by: Liang Yang <liang.yang@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson-gxl.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
index b3786cde963d..7dae1d7bf6b0 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
@@ -617,8 +617,8 @@ static const char * const sdio_groups[] = {
};
static const char * const nand_groups[] = {
- "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle",
- "nand_wen_clk", "nand_ren_wr", "nand_dqs",
+ "emmc_nand_d07", "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale",
+ "nand_cle", "nand_wen_clk", "nand_ren_wr", "nand_dqs",
};
static const char * const uart_a_groups[] = {