diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2022-01-13 09:57:48 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2022-01-13 09:57:48 -0600 |
| commit | 96fe57938406c37507e90da1ac2f325458798025 (patch) | |
| tree | 2c8669cded285aa5cddf557e6f1c014eeadeabf5 /drivers/pci | |
| parent | fd785c64f3554a15a70a27486f81d38af397feca (diff) | |
| parent | ab344fd43f2958726d17d651c0cb692c67dca382 (diff) | |
Merge branch 'remotes/lorenzo/pci/mediatek-gen3'
- Disable Mediatek DVFSRC voltage request since lack of DVFSRC to respond
to the request causes failure to exit L1 PM Substate (Jianjun Wang)
* remotes/lorenzo/pci/mediatek-gen3:
PCI: mediatek-gen3: Disable DVFSRC voltage request
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/controller/pcie-mediatek-gen3.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 17c59b0d6978..21207df680cc 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -79,6 +79,9 @@ #define PCIE_ICMD_PM_REG 0x198 #define PCIE_TURN_OFF_LINK BIT(4) +#define PCIE_MISC_CTRL_REG 0x348 +#define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1) + #define PCIE_TRANS_TABLE_BASE_REG 0x800 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4 #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8 @@ -297,6 +300,11 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port) val &= ~PCIE_INTX_ENABLE; writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); + /* Disable DVFSRC voltage request */ + val = readl_relaxed(port->base + PCIE_MISC_CTRL_REG); + val |= PCIE_DISABLE_DVFSRC_VLT_REQ; + writel_relaxed(val, port->base + PCIE_MISC_CTRL_REG); + /* Assert all reset signals */ val = readl_relaxed(port->base + PCIE_RST_CTRL_REG); val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; |