diff options
| author | Ping-Ke Shih <pkshih@realtek.com> | 2024-03-29 09:52:51 +0800 |
|---|---|---|
| committer | Ping-Ke Shih <pkshih@realtek.com> | 2024-04-03 10:43:02 +0800 |
| commit | a78d33a1286ccba088e422720e00f36b2d76dd7d (patch) | |
| tree | fbfef9b22533c4d1083fd96607e086bca115d6f2 /drivers/net/wireless/realtek/rtw89/pci.h | |
| parent | 5b919d726b613c78d4dc463dd9f90c55843fd1b3 (diff) | |
wifi: rtw89: 8852c: disable PCI PHY EQ to improve compatibility
For adaption EQ circuit, this HW design and affected by EIEOS (Electrical
Idle Exit Order Set) amplitude from platform and process from IC, so
disable EQ to improve that.
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://msgid.link/20240329015251.22762-5-pkshih@realtek.com
Diffstat (limited to 'drivers/net/wireless/realtek/rtw89/pci.h')
| -rw-r--r-- | drivers/net/wireless/realtek/rtw89/pci.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/net/wireless/realtek/rtw89/pci.h b/drivers/net/wireless/realtek/rtw89/pci.h index 87e7081664c1..7666753ae983 100644 --- a/drivers/net/wireless/realtek/rtw89/pci.h +++ b/drivers/net/wireless/realtek/rtw89/pci.h @@ -12,11 +12,18 @@ #define MDIO_PG0_G2 2 #define MDIO_PG1_G2 3 #define RAC_CTRL_PPR 0x00 +#define RAC_ANA03 0x03 +#define OOBS_SEN_MASK GENMASK(5, 1) +#define RAC_ANA09 0x09 +#define BAC_OOBS_SEL BIT(4) #define RAC_ANA0A 0x0A #define B_BAC_EQ_SEL BIT(5) #define RAC_ANA0C 0x0C #define B_PCIE_BIT_PSAVE BIT(15) +#define RAC_ANA0D 0x0D +#define BAC_RX_TEST_EN BIT(6) #define RAC_ANA10 0x10 +#define ADDR_SEL_PINOUT_DIS_VAL 0x3C4 #define B_PCIE_BIT_PINOUT_DIS BIT(3) #define RAC_REG_REV2 0x1B #define BAC_CMU_EN_DLY_MASK GENMASK(15, 12) @@ -30,6 +37,7 @@ #define RAC_ANA1E_G1_VAL 0x66EA #define RAC_ANA1E_G2_VAL 0x6EEA #define RAC_ANA1F 0x1F +#define OOBS_LEVEL_MASK GENMASK(12, 8) #define RAC_ANA24 0x24 #define B_AX_DEGLITCH GENMASK(11, 8) #define RAC_ANA26 0x26 |