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authorPing-Ke Shih <pkshih@realtek.com>2024-02-02 11:06:42 +0800
committerKalle Valo <kvalo@kernel.org>2024-02-06 20:05:23 +0200
commit4dbd964f33aab6f99891b9610ad4b36cc215be0d (patch)
tree9d9e006454ba0f90b3416c39714388151fae45cd /drivers/net/wireless/realtek/rtw89/mac.h
parent7e2629dc843fb46f0b8b3aba44708b508f6f98cf (diff)
wifi: rtw89: 8922a: add chip_ops::rfk_hw_init
Add a chip_ops for WiFi 7 chips to set additional RF configurations including MLO and PLL settings. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://msgid.link/20240202030642.108385-12-pkshih@realtek.com
Diffstat (limited to 'drivers/net/wireless/realtek/rtw89/mac.h')
-rw-r--r--drivers/net/wireless/realtek/rtw89/mac.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/wireless/realtek/rtw89/mac.h b/drivers/net/wireless/realtek/rtw89/mac.h
index b3fe4cab6d3a..7aea57804e93 100644
--- a/drivers/net/wireless/realtek/rtw89/mac.h
+++ b/drivers/net/wireless/realtek/rtw89/mac.h
@@ -1328,6 +1328,7 @@ enum rtw89_mac_xtal_si_offset {
#define XTAL_SI_BIG_PWR_CUT BIT(1)
XTAL_SI_XTAL_DRV = 0x15,
#define XTAL_SI_DRV_LATCH BIT(4)
+ XTAL_SI_XTAL_PLL = 0x16,
XTAL_SI_XTAL_XMD_2 = 0x24,
#define XTAL_SI_LDO_LPS GENMASK(6, 4)
XTAL_SI_XTAL_XMD_4 = 0x26,
@@ -1361,6 +1362,7 @@ enum rtw89_mac_xtal_si_offset {
XTAL_SI_SRAM_CTRL = 0xA1,
#define XTAL_SI_SRAM_DIS BIT(1)
#define FULL_BIT_MASK GENMASK(7, 0)
+ XTAL_SI_APBT = 0xD1,
XTAL_SI_PLL = 0xE0,
XTAL_SI_PLL_1 = 0xE1,
};