diff options
| author | Ching-Te Ku <ku920601@realtek.com> | 2020-11-09 16:58:59 +0800 |
|---|---|---|
| committer | Kalle Valo <kvalo@codeaurora.org> | 2020-11-10 20:58:08 +0200 |
| commit | 3f3fef5f6a8ff96f1bd7fc65a76fbe4ccc87b14a (patch) | |
| tree | 41349582b73c14db3764e3f9601ad03321e431a2 /drivers/net/wireless/realtek/rtw88/rtw8723d.c | |
| parent | dd90fc4630d285db429e393522d7b3844fbf79e9 (diff) | |
rtw88: coex: fixed some wrong register definition and setting
Some register definition and bit definition were incorrect.
e.g. REG_BT_COEX_V2 should be word alignment to meet the coding style.
e.g. set REG_BT_TDMA_TIME[5:0]=0x5,
But the original is to set REG_BT_TDMA_TIME[7:0]=0x5.
This will cause unexpected hardware behavior.
Signed-off-by: Ching-Te Ku <ku920601@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20201109085909.9143-2-pkshih@realtek.com
Diffstat (limited to 'drivers/net/wireless/realtek/rtw88/rtw8723d.c')
| -rw-r--r-- | drivers/net/wireless/realtek/rtw88/rtw8723d.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/wireless/realtek/rtw88/rtw8723d.c b/drivers/net/wireless/realtek/rtw88/rtw8723d.c index 832dc8e98bee..84d66b5c2733 100644 --- a/drivers/net/wireless/realtek/rtw88/rtw8723d.c +++ b/drivers/net/wireless/realtek/rtw88/rtw8723d.c @@ -1506,14 +1506,14 @@ static void rtw8723d_coex_cfg_init(struct rtw_dev *rtwdev) /* BT report packet sample rate */ /* 0x790[5:0]=0x5 */ - rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05); + rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); /* enable BT counter statistics */ rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); /* enable PTA (3-wire function form BT side) */ rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); - rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3); + rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); /* enable PTA (tx/rx signal form WiFi side) */ rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); |