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authorWolfram Sang <wsa+renesas@sang-engineering.com>2022-04-04 12:05:08 +0200
committerUlf Hansson <ulf.hansson@linaro.org>2022-04-04 13:46:10 +0200
commit46d4820f949a3030b19ee482c68a50b06dd27590 (patch)
treea633d9efa264ebef1def04887aec2153489ef91e /drivers/mmc/core/queue.c
parent08ebf903af57cda6d773f3dd1671b64f73b432b8 (diff)
mmc: renesas_sdhi: special 4tap settings only apply to HS400
Previous documentation was vague, so we included SDR104 for slow SDnH clock settings. It turns out now, that it is only needed for HS400. Fixes: bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling") Cc: stable@vger.kernel.org Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220404100508.3209-1-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/core/queue.c')
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