diff options
| author | Stefan Popa <stefan.popa@analog.com> | 2019-06-24 18:13:56 +0300 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2019-06-26 21:24:21 +0100 |
| commit | def914a4c3899b6b3705c8ea67d29972f5652a14 (patch) | |
| tree | bf58c895dda6b3075448ddcaaf68a9191023ce74 /drivers/iio/frequency | |
| parent | 84ed6482c6d889dcfa9c6b6e8b17c53748ab4f43 (diff) | |
iio: frequency: adf4371: Add support for output stage mute
Another feature of the ADF4371/ADF4372 is that the supply current to the
RF8P and RF8N output stage can shut down until the ADF4371 achieves lock
as measured by the digital lock detect circuitry. The mute to lock
detect bit (MUTE_LD) in REG25 enables this function.
Signed-off-by: Stefan Popa <stefan.popa@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'drivers/iio/frequency')
| -rw-r--r-- | drivers/iio/frequency/adf4371.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/iio/frequency/adf4371.c b/drivers/iio/frequency/adf4371.c index f874219fa8a2..e48f15cc9ab5 100644 --- a/drivers/iio/frequency/adf4371.c +++ b/drivers/iio/frequency/adf4371.c @@ -45,6 +45,10 @@ #define ADF4371_RF_DIV_SEL_MSK GENMASK(6, 4) #define ADF4371_RF_DIV_SEL(x) FIELD_PREP(ADF4371_RF_DIV_SEL_MSK, x) +/* ADF4371_REG25 */ +#define ADF4371_MUTE_LD_MSK BIT(7) +#define ADF4371_MUTE_LD(x) FIELD_PREP(ADF4371_MUTE_LD_MSK, x) + /* ADF4371_REG32 */ #define ADF4371_TIMEOUT_MSK GENMASK(1, 0) #define ADF4371_TIMEOUT(x) FIELD_PREP(ADF4371_TIMEOUT_MSK, x) @@ -484,6 +488,15 @@ static int adf4371_setup(struct adf4371_state *st) if (ret < 0) return ret; + /* Mute to Lock Detect */ + if (device_property_read_bool(&st->spi->dev, "adi,mute-till-lock-en")) { + ret = regmap_update_bits(st->regmap, ADF4371_REG(0x25), + ADF4371_MUTE_LD_MSK, + ADF4371_MUTE_LD(1)); + if (ret < 0) + return ret; + } + /* Set address in ascending order, so the bulk_write() will work */ ret = regmap_update_bits(st->regmap, ADF4371_REG(0x0), ADF4371_ADDR_ASC_MSK | ADF4371_ADDR_ASC_R_MSK, |