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author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2018-05-17 15:58:00 +1000 |
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committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2018-06-12 14:05:39 +1000 |
commit | 9f4a8a2d7f9d71093f41c4bb0ef8707e8145bad3 (patch) | |
tree | 3fe9e7189cb1fe1b709550926aee61405585a59f /drivers/fpga | |
parent | 52b7116e885e95a0d4206cca7f11ef332bb1dd89 (diff) |
fsi/sbefifo: Add driver for the SBE FIFO
This driver provides an in-kernel and a user API for accessing
the command FIFO of the SBE (Self Boot Engine) of the POWER9
processor, via the FSI bus.
It provides an in-kernel interface to submit command and receive
responses, along with a helper to locate and analyse the response
status block. It's a simple synchronous submit() type API.
The user interface uses the write/read interface that an earlier
version of this driver already provided, however it has some
specific limitations in order to keep the driver simple and
avoid using up a lot of kernel memory:
- The user should perform a single write() with the command and
a single read() to get the response (with a buffer big enough
to hold the entire response).
- On a write() the command is simply "stored" into a kernel buffer,
it is submitted as one operation on the subsequent read(). This
allows to have the code write directly from the FIFO into the user
buffer and avoid hogging the SBE between the write() and read()
syscall as it's critical that the SBE be freed asap to respond
to the host. An extra write() will simply replace the previously
written command.
- A write of a single 4 bytes containing the value 0x52534554
in big endian will trigger a reset request. No read is necessary,
the write() call will return when the reset has been acknowledged
or times out.
- The command is limited to 4K bytes.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Tested-by: Joel Stanley <joel@jms.id.au>
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Diffstat (limited to 'drivers/fpga')
0 files changed, 0 insertions, 0 deletions