diff options
| author | Alfonso Rodriguez <alfonso.rodriguezm@upm.es> | 2023-06-05 17:24:33 +0530 |
|---|---|---|
| committer | Xu Yilun <yilun.xu@intel.com> | 2023-06-06 19:14:19 +0800 |
| commit | 47147d56f92ee3f575e4b457413e0f2587b40e17 (patch) | |
| tree | 06335858a88728a6d725f99a4c5c51ee2eff1b09 /drivers/fpga | |
| parent | 148efa63bab383993a06770c2c05cfb9ed29a193 (diff) | |
fpga: zynq-fpga: Ensure proper xCAP interface switch
The Zynq platform has PCAP, ICAP and JTAG interfaces for configuring
programmable logic (PL). The existing driver implementation uses the
PCAP interface to configure the PL. Before switching the PL configuration
interface from PCAP to ICAP make sure that all outstanding Transactions
relevant to the PL configuration should be completed by the PCAP interface
otherwise it may lead to PL configuration issues.
This patch provides a required fix to ensure that all existing PL
transactions are completed before switching from PCAP to ICAP.
For detailed information relevant to PL configuration interfaces refer
Zynq 7000 TRM (section 6.5.1).
Link: https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM
Signed-off-by: Alfonso Rodriguez <alfonso.rodriguezm@upm.es>
Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
Acked-by: Xu Yilun <yilun.xu@intel.com>
Link: https://lore.kernel.org/r/20230605115433.186087-1-nava.kishore.manne@amd.com
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Diffstat (limited to 'drivers/fpga')
| -rw-r--r-- | drivers/fpga/zynq-fpga.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index ae0da361e6c6..f8214cae9b6e 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -493,15 +493,15 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, if (err) return err; - /* Release 'PR' control back to the ICAP */ - zynq_fpga_write(priv, CTRL_OFFSET, - zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); - err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, intr_status & IXR_PCFG_DONE_MASK, INIT_POLL_DELAY, INIT_POLL_TIMEOUT); + /* Release 'PR' control back to the ICAP */ + zynq_fpga_write(priv, CTRL_OFFSET, + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); + clk_disable(priv->clk); if (err) |