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| author | Dan Williams <dan.j.williams@intel.com> | 2021-06-15 16:18:11 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2021-06-15 16:46:34 -0700 |
| commit | 6af7139c979474a29a6ad642c9bf32d92e24c5bc (patch) | |
| tree | 8e971a9c4b6f2475858c80d5d0902a92994e680d /drivers/cxl/pmem.c | |
| parent | 87815ee9d0060a91bdf18266e42837a9adb5972e (diff) | |
cxl/core: Add cxl-bus driver infrastructure
Enable devices on the 'cxl' bus to be attached to drivers. The initial
user of this functionality is a driver for an 'nvdimm-bridge' device
that anchors a libnvdimm hierarchy attached to CXL persistent memory
resources. Other device types that will leverage this include:
cxl_port: map and use component register functionality (HDM Decoders)
cxl_nvdimm: translate CXL memory expander endpoints to libnvdimm
'nvdimm' objects
cxl_region: translate CXL interleave sets to libnvdimm 'region' objects
The pairing of devices to drivers is handled through the cxl_device_id()
matching to cxl_driver.id values. A cxl_device_id() of '0' indicates no
driver support.
In addition to ->match(), ->probe(), and ->remove() support for the
'cxl' bus introduce MODULE_ALIAS_CXL() to autoload modules containing
cxl-drivers. Drivers are added in follow-on changes.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/162379909190.2993820.6134168109678004186.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/pmem.c')
0 files changed, 0 insertions, 0 deletions