diff options
| author | Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> | 2022-07-01 09:27:20 +0300 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-07-06 15:20:58 -0500 |
| commit | 74d40ace3f08ce4d81b4a7e5d4d87a7294f55d36 (patch) | |
| tree | 1112f432111ac7731690f402e17b1618843c7de0 /drivers/clk | |
| parent | 94bed9bb05c7850ff5d80b87cc29004901f37956 (diff) | |
clk: qcom: clk-alpha-pll: limit exported symbols to GPL licensed code
Unify all exported PLL clock configuration functions and data structures
as GPL symbols.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220701062720.2757874-1-vladimir.zapolskiy@linaro.org
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/qcom/clk-alpha-pll.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 288692f0ea39..47879ee5a677 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1823,7 +1823,7 @@ const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { .round_rate = clk_alpha_pll_round_rate, .set_rate = alpha_pll_lucid_5lpe_set_rate, }; -EXPORT_SYMBOL(clk_alpha_pll_lucid_5lpe_ops); +EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops); const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { .enable = alpha_pll_lucid_5lpe_enable, @@ -1832,14 +1832,14 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { .recalc_rate = clk_trion_pll_recalc_rate, .round_rate = clk_alpha_pll_round_rate, }; -EXPORT_SYMBOL(clk_alpha_pll_fixed_lucid_5lpe_ops); +EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops); const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, }; -EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops); +EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) @@ -1992,7 +1992,7 @@ const struct clk_ops clk_alpha_pll_zonda_ops = { .round_rate = clk_alpha_pll_round_rate, .set_rate = clk_zonda_pll_set_rate, }; -EXPORT_SYMBOL(clk_alpha_pll_zonda_ops); +EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) { |