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authorJernej Skrabec <jernej.skrabec@siol.net>2018-08-09 18:52:13 +0200
committerMaxime Ripard <maxime.ripard@bootlin.com>2018-08-27 09:18:01 +0200
commitcb54fbd21a8fd97c2a82a069e8c80abdedbeb530 (patch)
tree90a2ebc3f6afe2e5b550b65765b8b8cb1adfa5b2 /drivers/clk/sunxi-ng/ccu_nm.h
parent58c0f79887d5e425fe6a9fd542778e50df69e9c6 (diff)
clk: sunxi-ng: Add maximum rate constraint to NM PLLs
On some NM PLLs, frequency can be set above PLL working range. Add a constraint for maximum supported rate. This way, drivers can specify which is maximum allowed rate for PLL. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu_nm.h')
-rw-r--r--drivers/clk/sunxi-ng/ccu_nm.h30
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h
index 1d8b459c50b7..de232f2199a6 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.h
+++ b/drivers/clk/sunxi-ng/ccu_nm.h
@@ -38,6 +38,7 @@ struct ccu_nm {
unsigned int fixed_post_div;
unsigned int min_rate;
+ unsigned int max_rate;
struct ccu_common common;
};
@@ -115,6 +116,35 @@ struct ccu_nm {
}, \
}
+#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name, \
+ _parent, _reg, \
+ _min_rate, _max_rate, \
+ _nshift, _nwidth, \
+ _mshift, _mwidth, \
+ _frac_en, _frac_sel, \
+ _frac_rate_0, \
+ _frac_rate_1, \
+ _gate, _lock, _flags) \
+ struct ccu_nm _struct = { \
+ .enable = _gate, \
+ .lock = _lock, \
+ .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
+ .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
+ .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \
+ _frac_rate_0, \
+ _frac_rate_1), \
+ .min_rate = _min_rate, \
+ .max_rate = _max_rate, \
+ .common = { \
+ .reg = _reg, \
+ .features = CCU_FEATURE_FRACTIONAL, \
+ .hw.init = CLK_HW_INIT(_name, \
+ _parent, \
+ &ccu_nm_ops, \
+ _flags), \
+ }, \
+ }
+
#define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \
_nshift, _nwidth, \
_mshift, _mwidth, \