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authorGuru Das Srinagesh <gurus@codeaurora.org>2020-06-02 15:31:15 -0700
committerThierry Reding <thierry.reding@gmail.com>2020-06-17 20:42:10 +0200
commita6733474ba4bf3150120bacc1d2db446d89d3dbe (patch)
tree9b7b771eab79949e44e0720397b986d8f8a66620 /drivers/clk/clk-pwm.c
parent134ada17dbad272cdca57f2819a796c87e352274 (diff)
clk: pwm: Use 64-bit division function
Since the PWM framework is switching struct pwm_args.period's datatype to u64, prepare for this transition by using div64_u64() to handle a 64-bit divisor. Also ensure that divide-by-zero (with fixed_rate as denominator) does not happen with an explicit check with probe failure as a consequence. Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/clk/clk-pwm.c')
-rw-r--r--drivers/clk/clk-pwm.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/clk/clk-pwm.c b/drivers/clk/clk-pwm.c
index 87fe0b0e01a3..86f2e2d3fc02 100644
--- a/drivers/clk/clk-pwm.c
+++ b/drivers/clk/clk-pwm.c
@@ -89,7 +89,12 @@ static int clk_pwm_probe(struct platform_device *pdev)
}
if (of_property_read_u32(node, "clock-frequency", &clk_pwm->fixed_rate))
- clk_pwm->fixed_rate = NSEC_PER_SEC / pargs.period;
+ clk_pwm->fixed_rate = div64_u64(NSEC_PER_SEC, pargs.period);
+
+ if (!clk_pwm->fixed_rate) {
+ dev_err(&pdev->dev, "fixed_rate cannot be zero\n");
+ return -EINVAL;
+ }
if (pargs.period != NSEC_PER_SEC / clk_pwm->fixed_rate &&
pargs.period != DIV_ROUND_UP(NSEC_PER_SEC, clk_pwm->fixed_rate)) {