diff options
| author | Joerg Roedel <jroedel@suse.de> | 2020-09-07 15:15:20 +0200 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2020-09-07 19:45:25 +0200 |
| commit | 29dcc60f6a19fb0aaee97bd1ae2ed8a7dc6f0cfe (patch) | |
| tree | 9bcd688e264f130c2928fa2a92e6729c6cd7c372 /arch/x86/boot/compressed/idt_64.c | |
| parent | 21cf2372618ef167d8c4ae04880fb873b55b2daa (diff) | |
x86/boot/compressed/64: Add stage1 #VC handler
Add the first handler for #VC exceptions. At stage 1 there is no GHCB
yet because the kernel might still be running on the EFI page table.
The stage 1 handler is limited to the MSR-based protocol to talk to the
hypervisor and can only support CPUID exit-codes, but that is enough to
get to stage 2.
[ bp: Zap superfluous newlines after rd/wrmsr instruction mnemonics. ]
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20200907131613.12703-20-joro@8bytes.org
Diffstat (limited to 'arch/x86/boot/compressed/idt_64.c')
| -rw-r--r-- | arch/x86/boot/compressed/idt_64.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/boot/compressed/idt_64.c b/arch/x86/boot/compressed/idt_64.c index 5f083092a86d..f3ca7324be44 100644 --- a/arch/x86/boot/compressed/idt_64.c +++ b/arch/x86/boot/compressed/idt_64.c @@ -32,6 +32,10 @@ void load_stage1_idt(void) { boot_idt_desc.address = (unsigned long)boot_idt; + + if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) + set_idt_entry(X86_TRAP_VC, boot_stage1_vc); + load_boot_idt(&boot_idt_desc); } |