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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2022-02-22 10:04:28 +0100
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2022-03-01 10:07:22 +0100
commit455481fc9a807798eca05f6fb0918ab88109d845 (patch)
tree6dca8dd1d049a4e09b3f750d97fe8cb5035feadb /arch/mips/mm/tlb-r3k.c
parentfbb1d4b381b058ed60b39f1598532f559b441762 (diff)
MIPS: Remove TX39XX support
No (active) developer owns this hardware, so let's remove Linux support. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Diffstat (limited to 'arch/mips/mm/tlb-r3k.c')
-rw-r--r--arch/mips/mm/tlb-r3k.c40
1 files changed, 2 insertions, 38 deletions
diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c
index a36622ebea55..53dfa2b9316b 100644
--- a/arch/mips/mm/tlb-r3k.c
+++ b/arch/mips/mm/tlb-r3k.c
@@ -36,8 +36,6 @@ extern void build_tlb_refill_handler(void);
"nop\n\t" \
".set pop\n\t")
-int r3k_have_wired_reg; /* Should be in cpu_data? */
-
/* TLB operations. */
static void local_flush_tlb_from(int entry)
{
@@ -62,7 +60,7 @@ void local_flush_tlb_all(void)
printk("[tlball]");
#endif
local_irq_save(flags);
- local_flush_tlb_from(r3k_have_wired_reg ? read_c0_wired() : 8);
+ local_flush_tlb_from(8);
local_irq_restore(flags);
}
@@ -224,34 +222,7 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
unsigned long old_ctx;
static unsigned long wired = 0;
- if (r3k_have_wired_reg) { /* TX39XX */
- unsigned long old_pagemask;
- unsigned long w;
-
-#ifdef DEBUG_TLB
- printk("[tlbwired<entry lo0 %8x, hi %8x\n, pagemask %8x>]\n",
- entrylo0, entryhi, pagemask);
-#endif
-
- local_irq_save(flags);
- /* Save old context and create impossible VPN2 value */
- old_ctx = read_c0_entryhi() & asid_mask;
- old_pagemask = read_c0_pagemask();
- w = read_c0_wired();
- write_c0_wired(w + 1);
- write_c0_index(w << 8);
- write_c0_pagemask(pagemask);
- write_c0_entryhi(entryhi);
- write_c0_entrylo0(entrylo0);
- BARRIER;
- tlb_write_indexed();
-
- write_c0_entryhi(old_ctx);
- write_c0_pagemask(old_pagemask);
- local_flush_tlb_all();
- local_irq_restore(flags);
-
- } else if (wired < 8) {
+ if (wired < 8) {
#ifdef DEBUG_TLB
printk("[tlbwired<entry lo0 %8x, hi %8x\n>]\n",
entrylo0, entryhi);
@@ -272,13 +243,6 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
void tlb_init(void)
{
- switch (current_cpu_type()) {
- case CPU_TX3922:
- case CPU_TX3927:
- r3k_have_wired_reg = 1;
- write_c0_wired(0); /* Set to 8 on reset... */
- break;
- }
local_flush_tlb_from(0);
build_tlb_refill_handler();
}