diff options
| author | Sonic Zhang <sonic.zhang@analog.com> | 2012-06-29 18:19:29 +0800 |
|---|---|---|
| committer | Bob Liu <lliubbo@gmail.com> | 2012-07-24 13:39:52 +0800 |
| commit | e0a593104d43dc98250984daa1b82f964835fcfa (patch) | |
| tree | ed8202bb9b2ab089871cd9d87c455c97ae496f4f /arch/blackfin/mach-common | |
| parent | 11b27cb5b97319bae0a1604ddac85b9b08802a7e (diff) | |
bf60x: sec: Enable sec interrupt source priority configuration.
Customize the SEC interrupt priority array in machine ints-priority.c.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Diffstat (limited to 'arch/blackfin/mach-common')
| -rw-r--r-- | arch/blackfin/mach-common/ints-priority.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index a7e97a3607da..5a109a184021 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c @@ -310,6 +310,23 @@ static void bfin_sec_disable(struct irq_data *d) hard_local_irq_restore(flags); } +static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority) +{ + unsigned long flags = hard_local_irq_save(); + uint32_t reg_sctl; + int i; + + bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels); + + for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) { + reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO; + reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET; + bfin_write_SEC_SCTL(i, reg_sctl); + } + + hard_local_irq_restore(flags); +} + static void bfin_sec_raise_irq(unsigned int sid) { unsigned long flags = hard_local_irq_save(); @@ -1534,6 +1551,10 @@ int __init init_arch_irq(void) printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); + bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority); + + bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority); + /* Enable interrupts IVG7-15 */ bfin_irq_flags |= IMASK_IVG15 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | |