diff options
| author | Thierry Reding <treding@nvidia.com> | 2023-08-17 16:14:05 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2023-10-10 17:37:35 +0200 |
| commit | 036f15c24888cb823e3cb47e7bdffd827387518e (patch) | |
| tree | a2329fc0282d14d681b0f69d11417abc9080af9d /arch/arm64/boot/dts/nvidia | |
| parent | 4bf7fa33d10b99b4cc9ac15693128ef2ced7142c (diff) | |
arm64: tegra: Use correct format for clocks property
phandle and clock specifier pairs should be enclosed in angular
brackets.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra234.dtsi | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 95524e5bce82..923850ca6771 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -705,8 +705,8 @@ #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; - clocks = <&bpmp TEGRA234_CLK_I2C1 - &bpmp TEGRA234_CLK_PLLP_OUT0>; + clocks = <&bpmp TEGRA234_CLK_I2C1>, + <&bpmp TEGRA234_CLK_PLLP_OUT0>; assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; clock-names = "div-clk", "parent"; @@ -724,8 +724,8 @@ #size-cells = <0>; status = "disabled"; clock-frequency = <400000>; - clocks = <&bpmp TEGRA234_CLK_I2C3 - &bpmp TEGRA234_CLK_PLLP_OUT0>; + clocks = <&bpmp TEGRA234_CLK_I2C3>, + <&bpmp TEGRA234_CLK_PLLP_OUT0>; assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; clock-names = "div-clk", "parent"; @@ -743,8 +743,8 @@ #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; - clocks = <&bpmp TEGRA234_CLK_I2C4 - &bpmp TEGRA234_CLK_PLLP_OUT0>; + clocks = <&bpmp TEGRA234_CLK_I2C4>, + <&bpmp TEGRA234_CLK_PLLP_OUT0>; assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; clock-names = "div-clk", "parent"; @@ -762,8 +762,8 @@ #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; - clocks = <&bpmp TEGRA234_CLK_I2C6 - &bpmp TEGRA234_CLK_PLLP_OUT0>; + clocks = <&bpmp TEGRA234_CLK_I2C6>, + <&bpmp TEGRA234_CLK_PLLP_OUT0>; assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; clock-names = "div-clk", "parent"; @@ -781,8 +781,8 @@ #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; - clocks = <&bpmp TEGRA234_CLK_I2C7 - &bpmp TEGRA234_CLK_PLLP_OUT0>; + clocks = <&bpmp TEGRA234_CLK_I2C7>, + <&bpmp TEGRA234_CLK_PLLP_OUT0>; assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; clock-names = "div-clk", "parent"; @@ -807,8 +807,8 @@ #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; - clocks = <&bpmp TEGRA234_CLK_I2C9 - &bpmp TEGRA234_CLK_PLLP_OUT0>; + clocks = <&bpmp TEGRA234_CLK_I2C9>, + <&bpmp TEGRA234_CLK_PLLP_OUT0>; assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; clock-names = "div-clk", "parent"; @@ -1751,8 +1751,8 @@ #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; - clocks = <&bpmp TEGRA234_CLK_I2C2 - &bpmp TEGRA234_CLK_PLLP_OUT0>; + clocks = <&bpmp TEGRA234_CLK_I2C2>, + <&bpmp TEGRA234_CLK_PLLP_OUT0>; clock-names = "div-clk", "parent"; assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; @@ -1770,8 +1770,8 @@ #size-cells = <0>; status = "disabled"; clock-frequency = <400000>; - clocks = <&bpmp TEGRA234_CLK_I2C8 - &bpmp TEGRA234_CLK_PLLP_OUT0>; + clocks = <&bpmp TEGRA234_CLK_I2C8>, + <&bpmp TEGRA234_CLK_PLLP_OUT0>; clock-names = "div-clk", "parent"; assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; |