diff options
| author | Adam Ford <aford173@gmail.com> | 2022-04-26 15:51:43 -0500 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2022-05-05 11:53:20 +0800 |
| commit | 4ce01ce36d77137cf60776b320babed89de6bd4c (patch) | |
| tree | 83e76e0458a2951bdc0ab1978eb9860e6861374c /arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi | |
| parent | 42c1a6f62e5c46269ed37238f6a5331b30c32c75 (diff) | |
arm64: dts: imx8mm-beacon: Enable RTS-CTS on UART3
There is a header for a DB9 serial port, but any attempts to use
hardware handshaking fail. Enable RTS and CTS pin muxing and enable
handshaking in the uart node.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index ec3f2c177035..f338a886d811 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -278,6 +278,7 @@ pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clk IMX8MM_CLK_UART3>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + uart-has-rtscts; status = "okay"; }; @@ -386,6 +387,8 @@ fsl,pins = < MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40 + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40 >; }; |