diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2021-11-22 09:10:03 -0600 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2021-12-27 04:20:06 -0600 |
| commit | 36de991e93908f7ad5c2a0eac9c4ecf8b723fa4a (patch) | |
| tree | 5f15180537ae389dd70153ce8972ff55b5125259 /arch/arm64/boot/dts/altera | |
| parent | f34e8875ae244462711e31fcc4a82db13a16d36f (diff) | |
ARM: dts: socfpga: change qspi to "intel,socfpga-qspi"
Because of commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling"),
which does a write to the CQSPI_REG_WR_COMPLETION_CTRL register
regardless of any condition. Well, the Cadence QuadSPI controller on
Intel's SoCFPGA platforms does not implement the
CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
results in a crash!
So starting with v5.16, I introduced the patch
98d948eb833 ("spi: cadence-quadspi: fix write completion support"),
which adds the dts compatible "intel,socfpga-qspi" that is specific for
versions that doesn't have the CQSPI_REG_WR_COMPLETION_CTRL register implemented.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v3: revert back to "intel,socfpga-qspi"
v2: use both "cdns,qspi-nor" and "cdns,qspi-nor-0010"
Diffstat (limited to 'arch/arm64/boot/dts/altera')
| -rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index d301ac0d406b..3ec301bd08a9 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -594,7 +594,7 @@ }; qspi: spi@ff8d2000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff8d2000 0x100>, |