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authorDavid Lechner <david@lechnology.com>2018-01-06 21:10:15 -0600
committerSekhar Nori <nsekhar@ti.com>2018-02-19 16:25:15 +0530
commit94f2e94514e5dea6677b4379efd3479105519bdc (patch)
tree8a349e5a86204d4514507b8238dc4c54283a8c8c /arch/arm/mach-davinci/time.c
parentbdec5a6b57896da81bc47262868468717a06bb69 (diff)
ARM: davinci: remove watchdog reset
This removes the watchdog reset code. The reset has been moved to drivers/watchdog/davinci_wdt.c. The watchdog driver registers the reset with the kernel so defining a reset for each machine is no longer needed. Signed-off-by: David Lechner <david@lechnology.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'arch/arm/mach-davinci/time.c')
-rw-r--r--arch/arm/mach-davinci/time.c57
1 files changed, 0 insertions, 57 deletions
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 034f865fe78e..1bb991ad9c1e 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -80,13 +80,6 @@ enum {
#define TGCR_UNRESET 0x1
#define TGCR_RESET_MASK 0x3
-#define WDTCR_WDEN_SHIFT 14
-#define WDTCR_WDEN_DISABLE 0x0
-#define WDTCR_WDEN_ENABLE 0x1
-#define WDTCR_WDKEY_SHIFT 16
-#define WDTCR_WDKEY_SEQ0 0xa5c6
-#define WDTCR_WDKEY_SEQ1 0xda7e
-
struct timer_s {
char *name;
unsigned int id;
@@ -409,53 +402,3 @@ void __init davinci_timer_init(void)
for (i=0; i< ARRAY_SIZE(timers); i++)
timer32_config(&timers[i]);
}
-
-/* reset board using watchdog timer */
-void davinci_watchdog_reset(struct platform_device *pdev)
-{
- u32 tgcr, wdtcr;
- void __iomem *base;
- struct clk *wd_clk;
-
- base = ioremap(pdev->resource[0].start, SZ_4K);
- if (WARN_ON(!base))
- return;
-
- wd_clk = clk_get(&pdev->dev, NULL);
- if (WARN_ON(IS_ERR(wd_clk)))
- return;
- clk_prepare_enable(wd_clk);
-
- /* disable, internal clock source */
- __raw_writel(0, base + TCR);
-
- /* reset timer, set mode to 64-bit watchdog, and unreset */
- tgcr = 0;
- __raw_writel(tgcr, base + TGCR);
- tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
- tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
- (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
- __raw_writel(tgcr, base + TGCR);
-
- /* clear counter and period regs */
- __raw_writel(0, base + TIM12);
- __raw_writel(0, base + TIM34);
- __raw_writel(0, base + PRD12);
- __raw_writel(0, base + PRD34);
-
- /* put watchdog in pre-active state */
- wdtcr = __raw_readl(base + WDTCR);
- wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
- (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
- __raw_writel(wdtcr, base + WDTCR);
-
- /* put watchdog in active state */
- wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
- (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
- __raw_writel(wdtcr, base + WDTCR);
-
- /* write an invalid value to the WDKEY field to trigger
- * a watchdog reset */
- wdtcr = 0x00004000;
- __raw_writel(wdtcr, base + WDTCR);
-}