diff options
author | Tony Lindgren <tony@atomide.com> | 2024-03-27 09:10:37 +0200 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2024-04-10 09:15:40 +0300 |
commit | a0a621533fe796d5a92ece5573663cb25bec470c (patch) | |
tree | ffe1f50b2cc4403af716e8a1b1c1ecf9ae14578e /arch/arm/boot/dts/ti | |
parent | de36994d7639024cde1f7d1dd6d9d69e7243572f (diff) |
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_IVA
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/ti')
-rw-r--r-- | arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi index e4f15453adfa..88c14c172b0f 100644 --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -426,13 +426,21 @@ clock-div = <1>; }; - dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_iva_byp_mux"; - clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x01ac>; + /* CM_CLKSEL_DPLL_IVA */ + clock@1ac { + compatible = "ti,clksel"; + reg = <0x1ac>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + dpll_iva_byp_mux: clock@23 { + reg = <23>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_iva_byp_mux"; + clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; + #clock-cells = <0>; + }; }; dpll_iva_ck: clock@1a0 { |