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authorWANG Xuerui <git@xen0n.name>2020-05-30 15:32:43 +0800
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2020-05-31 10:54:35 +0200
commitdd25ed7361fb543d32f0da66e1e492563e64938e (patch)
tree0837ff32dd22a0a74ede457907c490f16ab18b7d
parentf06da27eb82e358ca389ccb9d13de61e94e77a47 (diff)
MIPS: Loongson64: Reorder CPUCFG model match arms
Originally the match arms are ordered by model release date, however the LOONGSON_64R cores are even more reduced capability-wise. So put them at top of the switch block. Suggested-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
-rw-r--r--arch/mips/loongson64/cpucfg-emul.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/mips/loongson64/cpucfg-emul.c b/arch/mips/loongson64/cpucfg-emul.c
index ca75f07252df..cd619b47ba1f 100644
--- a/arch/mips/loongson64/cpucfg-emul.c
+++ b/arch/mips/loongson64/cpucfg-emul.c
@@ -137,6 +137,22 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
/* Add CPUCFG features non-discoverable otherwise. */
switch (c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) {
+ case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
+ case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
+ case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
+ case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
+ decode_loongson_config6(c);
+ probe_uca(c);
+
+ c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
+ LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC |
+ LOONGSON_CFG1_TGTSYNC);
+ c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
+ LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP |
+ LOONGSON_CFG2_LPM_REV2);
+ c->loongson3_cpucfg_data[2] = 0;
+ break;
+
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R1:
c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
@@ -164,22 +180,6 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
LOONGSON_CFG3_LCAMVW_REV1);
break;
- case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
- case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
- case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
- case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
- decode_loongson_config6(c);
- probe_uca(c);
-
- c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
- LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC |
- LOONGSON_CFG1_TGTSYNC);
- c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
- LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP |
- LOONGSON_CFG2_LPM_REV2);
- c->loongson3_cpucfg_data[2] = 0;
- break;
-
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0:
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_1:
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_0: