diff options
| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2019-12-08 19:05:24 +0100 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2019-12-11 11:26:26 -0800 |
| commit | c4ac5c37a4a5c5ce94f70542d006568bd4b7d685 (patch) | |
| tree | 7c8a374fdae23bc50063b4243bed9b3ed6a07b12 | |
| parent | 630ea3108adf0446b6b4194f3f42bc0bfe245d1d (diff) | |
ARM: dts: meson8: add the DDR clock controller
Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main
(HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the
inputs for the audio clock muxes.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| -rw-r--r-- | arch/arm/boot/dts/meson8.dtsi | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 4f59a4c8f036..257c1364864c 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -3,6 +3,7 @@ * Copyright 2014 Carlo Caione <carlo@caione.org> */ +#include <dt-bindings/clock/meson8-ddr-clkc.h> #include <dt-bindings/clock/meson8b-clkc.h> #include <dt-bindings/gpio/meson8-gpio.h> #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> @@ -195,6 +196,14 @@ #size-cells = <1>; ranges = <0x0 0xc8000000 0x8000>; + ddr_clkc: clock-controller@400 { + compatible = "amlogic,meson8-ddr-clkc"; + reg = <0x400 0x20>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + dmcbus: bus@6000 { compatible = "simple-bus"; reg = <0x6000 0x400>; @@ -455,8 +464,8 @@ &hhi { clkc: clock-controller { compatible = "amlogic,meson8-clkc"; - clocks = <&xtal>; - clock-names = "xtal"; + clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; + clock-names = "xtal", "ddr_pll"; #clock-cells = <1>; #reset-cells = <1>; }; |