diff options
| author | Thierry Reding <treding@nvidia.com> | 2019-06-13 18:12:24 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-06-25 16:10:28 -0700 |
| commit | c1139d20833f8882df608f456ce65b06cd1caa98 (patch) | |
| tree | 1df6bba7a7ccc83461c86c559aad6ae2a340ccea | |
| parent | 20675070127b51c6ca26a895c7e0b459f2c397e1 (diff) | |
clk: tegra: Warn if an enabled PLL is in IDDQ
A PLL in IDDQ doesn't work, whether it's enabled or not. This is not a
configuration that makes sense, so warn about it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | drivers/clk/tegra/clk-tegra210.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 51a21bf1715e..18384666b380 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -1014,8 +1014,12 @@ static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre) _pll_misc_chk_default(clk_base, pllre->params, 0, val, ~mask & PLLRE_MISC0_WRITE_MASK); - /* Enable lock detect */ + /* The PLL doesn't work if it's in IDDQ. */ val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]); + if (val & PLLRE_MISC0_IDDQ) + pr_warn("unexpected IDDQ bit set for enabled clock\n"); + + /* Enable lock detect */ val &= ~mask; val |= PLLRE_MISC0_DEFAULT_VALUE & mask; writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]); |