diff options
| author | Hendrik Brueckner <brueckner@linux.ibm.com> | 2018-08-29 17:46:06 +0200 |
|---|---|---|
| committer | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2019-02-22 09:19:52 +0100 |
| commit | 778fb10ccc18b16c022be898d8497767c20ea7b5 (patch) | |
| tree | f2d132f5f24d47f22be234d797ff46dd40c12b12 | |
| parent | 17bebcc68eeea3e1189f712dcba39809ad0d7a86 (diff) | |
s390/cpu_mf: add store cpu counter multiple instruction support
Add support for the STORE CPU COUNTER MULTIPLE instruction to extract
a range of counters from a counter set.
An assembler macro is used to create the instruction opcode because
the counter set identifier is part of the instruction and, thus,
cannot be easily specified as parameter.
Signed-off-by: Hendrik Brueckner <brueckner@linux.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
| -rw-r--r-- | arch/s390/include/asm/cpu_mf-insn.h | 22 | ||||
| -rw-r--r-- | arch/s390/include/asm/cpu_mf.h | 17 |
2 files changed, 39 insertions, 0 deletions
diff --git a/arch/s390/include/asm/cpu_mf-insn.h b/arch/s390/include/asm/cpu_mf-insn.h new file mode 100644 index 000000000000..a68b362e0964 --- /dev/null +++ b/arch/s390/include/asm/cpu_mf-insn.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for CPU-MF instructions + * + * Copyright IBM Corp. 2019 + * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com> + */ +#ifndef _ASM_S390_CPU_MF_INSN_H +#define _ASM_S390_CPU_MF_INSN_H + +#ifdef __ASSEMBLY__ + +/* Macro to generate the STCCTM instruction with a customized + * M3 field designating the counter set. + */ +.macro STCCTM r1 m3 db2 + .insn rsy,0xeb0000000017,\r1,\m3 & 0xf,\db2 +.endm + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/arch/s390/include/asm/cpu_mf.h b/arch/s390/include/asm/cpu_mf.h index bf2cbff926ef..53ba4f2ca296 100644 --- a/arch/s390/include/asm/cpu_mf.h +++ b/arch/s390/include/asm/cpu_mf.h @@ -12,6 +12,8 @@ #include <linux/errno.h> #include <asm/facility.h> +asm(".include \"asm/cpu_mf-insn.h\"\n"); + #define CPU_MF_INT_SF_IAE (1 << 31) /* invalid entry address */ #define CPU_MF_INT_SF_ISE (1 << 30) /* incorrect SDBT entry */ #define CPU_MF_INT_SF_PRA (1 << 29) /* program request alert */ @@ -209,6 +211,21 @@ static inline int ecctr(u64 ctr, u64 *val) return cc; } +/* Store CPU counter multiple for a particular counter set */ +static inline int stcctm(u8 set, u64 range, u64 *dest) +{ + int cc; + + asm volatile ( + " STCCTM %2,%3,%1\n" + " ipm %0\n" + " srl %0,28\n" + : "=d" (cc) + : "Q" (*dest), "d" (range), "i" (set) + : "cc", "memory"); + return cc; +} + /* Store CPU counter multiple for the MT utilization counter set */ static inline int stcctm5(u64 num, u64 *val) { |