diff options
| author | Mark Brown <broonie@kernel.org> | 2023-01-16 16:04:37 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2023-01-20 12:23:05 +0000 |
| commit | 6dabf1fac6b48d256b1d78b81c9356a88df26d2f (patch) | |
| tree | b9ee04e0de179326a37f8ad2e302f00d09a675e2 | |
| parent | ce514000da4f4b5f850f3339f805471e5c5c1caf (diff) | |
arm64: Document boot requirements for SME 2
SME 2 introduces the new ZT0 register, we require that access to this
reigster is not trapped when we identify that the feature is supported.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20221208-arm64-sme2-v4-2-f2fa0aef982f@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| -rw-r--r-- | Documentation/arm64/booting.rst | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index 96fe10ec6c24..f8d0a7288c73 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -369,6 +369,16 @@ Before jumping into the kernel, the following conditions must be met: - HCR_EL2.ATA (bit 56) must be initialised to 0b1. + For CPUs with the Scalable Matrix Extension version 2 (FEAT_SME2): + + - If EL3 is present: + + - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented |