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authorChris Metcalf <cmetcalf@tilera.com>2013-08-12 15:25:22 -0400
committerChris Metcalf <cmetcalf@tilera.com>2013-09-03 14:52:20 -0400
commit5e7705df28720c424c11bdedf0d568177351c55a (patch)
tree28c341353900c87e7ddcd097bb8e599070b3bbf7
parentbdb8205455a31362fc72075583aedd63ff0c944b (diff)
tile PCI RC: add comment about "PCI hole" problem
Explain the rationale of not overlapping the 64-bit DMA window with the PA range. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
-rw-r--r--arch/tile/include/asm/pci.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h
index c99ad44233f4..dfedd7ac7298 100644
--- a/arch/tile/include/asm/pci.h
+++ b/arch/tile/include/asm/pci.h
@@ -122,6 +122,11 @@ static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
* the CPA plus TILE_PCI_MEM_MAP_BASE_OFFSET. To support 32-bit
* devices, we create a separate map region that handles the low
* 4GB.
+ *
+ * This design lets us avoid the "PCI hole" problem where the host bridge
+ * won't pass DMA traffic with target addresses that happen to fall within the
+ * BAR space. This enables us to use all the physical memory for DMA, instead
+ * of wasting the same amount of physical memory as the BAR window size.
*/
#define TILE_PCI_MEM_MAP_BASE_OFFSET (1ULL << CHIP_PA_WIDTH())