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authorYann Gautier <yann.gautier@foss.st.com>2021-12-15 15:17:25 +0100
committerUlf Hansson <ulf.hansson@linaro.org>2021-12-21 13:06:10 +0100
commit4481ab602cedf93bd8fdb9ded6977dd4b14a27e3 (patch)
treeb61e8007f6ed40f934ffb3b27ee6ff18ce306cc1
parent5471fe8b383f82d9a20f8ac577c1f1cc3b9dbe5c (diff)
mmc: mmci: increase stm32 sdmmcv2 clock max freq
The variant->f_max is dependent on the IP, not on the SoC where it is embedded. Set the max frequency of its source clock to 267MHz. The frequency used will be limited by the IOs max frequency, set in the SoC device tree. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20211215141727.4901-3-yann.gautier@foss.st.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-rw-r--r--drivers/mmc/host/mmci.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index c0478dfa61b9..45b8608c935c 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -280,7 +280,7 @@ static struct variant_data variant_stm32_sdmmc = {
static struct variant_data variant_stm32_sdmmcv2 = {
.fifosize = 16 * 4,
.fifohalfsize = 8 * 4,
- .f_max = 208000000,
+ .f_max = 267000000,
.stm32_clkdiv = true,
.cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE,
.cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC,