diff options
| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2021-04-23 21:24:33 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2021-05-10 13:17:14 +0100 |
| commit | 1beb37b0e3f98708bfb37778049764b4500756da (patch) | |
| tree | 4e33a2d2e30d6568ea71604682cfbf764ea21b44 | |
| parent | 5edc24901f4d469f8fc943004f73655933e89dbf (diff) | |
spi: pxa2xx: Group Intel Quark specific definitions
DDS_RATE is Intel Quark specific definition. Move it to the rest
Intel Quark related.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20210423182441.50272-7-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | include/linux/pxa2xx_ssp.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h index 14b049840faf..1b6c1a0922bd 100644 --- a/include/linux/pxa2xx_ssp.h +++ b/include/linux/pxa2xx_ssp.h @@ -38,7 +38,6 @@ struct device_node; #define SSDR (0x10) /* SSP Data Write/Data Read Register */ #define SSTO (0x28) /* SSP Time Out Register */ -#define DDS_RATE (0x28) /* SSP DDS Clock Rate Register (Intel Quark) */ #define SSPSP (0x2C) /* SSP Programmable Serial Protocol */ #define SSTSA (0x30) /* SSP Tx Timeslot Active */ #define SSRSA (0x34) /* SSP Rx Timeslot Active */ @@ -105,6 +104,9 @@ struct device_node; #define CE4100_SSCR1_RFT GENMASK(11, 10) /* Receive FIFO Threshold (mask) */ #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */ +/* Intel Quark X1000 */ +#define DDS_RATE 0x28 /* SSP DDS Clock Rate Register */ + /* QUARK_X1000 SSCR0 bit definition */ #define QUARK_X1000_SSCR0_DSS GENMASK(4, 0) /* Data Size Select (mask) */ #define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */ |