blob: 8ed24d5fcff93c66adc2e68fe9ecc19464784e9e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef _UFS_MEDIATEK_H
#define _UFS_MEDIATEK_H
#include <linux/bitops.h>
#include <linux/soc/mediatek/mtk_sip_svc.h>
/*
* Vendor specific UFSHCI Registers
*/
#define REG_UFS_REFCLK_CTRL 0x144
#define REG_UFS_EXTREG 0x2100
#define REG_UFS_MPHYCTRL 0x2200
#define REG_UFS_REJECT_MON 0x22AC
#define REG_UFS_DEBUG_SEL 0x22C0
#define REG_UFS_PROBE 0x22C8
/*
* Ref-clk control
*
* Values for register REG_UFS_REFCLK_CTRL
*/
#define REFCLK_RELEASE 0x0
#define REFCLK_REQUEST BIT(0)
#define REFCLK_ACK BIT(1)
#define REFCLK_REQ_TIMEOUT_US 3000
/*
* Vendor specific pre-defined parameters
*/
#define UFS_MTK_LIMIT_NUM_LANES_RX 1
#define UFS_MTK_LIMIT_NUM_LANES_TX 1
#define UFS_MTK_LIMIT_HSGEAR_RX UFS_HS_G3
#define UFS_MTK_LIMIT_HSGEAR_TX UFS_HS_G3
#define UFS_MTK_LIMIT_PWMGEAR_RX UFS_PWM_G4
#define UFS_MTK_LIMIT_PWMGEAR_TX UFS_PWM_G4
#define UFS_MTK_LIMIT_RX_PWR_PWM SLOW_MODE
#define UFS_MTK_LIMIT_TX_PWR_PWM SLOW_MODE
#define UFS_MTK_LIMIT_RX_PWR_HS FAST_MODE
#define UFS_MTK_LIMIT_TX_PWR_HS FAST_MODE
#define UFS_MTK_LIMIT_HS_RATE PA_HS_MODE_B
#define UFS_MTK_LIMIT_DESIRED_MODE UFS_HS_MODE
/*
* Other attributes
*/
#define VS_DEBUGCLOCKENABLE 0xD0A1
#define VS_SAVEPOWERCONTROL 0xD0A6
#define VS_UNIPROPOWERDOWNCONTROL 0xD0A8
/*
* Vendor specific link state
*/
enum {
VS_LINK_DISABLED = 0,
VS_LINK_DOWN = 1,
VS_LINK_UP = 2,
VS_LINK_HIBERN8 = 3,
VS_LINK_LOST = 4,
VS_LINK_CFG = 5,
};
/*
* SiP commands
*/
#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276)
#define UFS_MTK_SIP_DEVICE_RESET BIT(1)
#define UFS_MTK_SIP_CRYPTO_CTRL BIT(2)
#define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3)
/*
* VS_DEBUGCLOCKENABLE
*/
enum {
TX_SYMBOL_CLK_REQ_FORCE = 5,
};
/*
* VS_SAVEPOWERCONTROL
*/
enum {
RX_SYMBOL_CLK_GATE_EN = 0,
SYS_CLK_GATE_EN = 2,
TX_CLK_GATE_EN = 3,
};
struct ufs_mtk_host {
struct ufs_hba *hba;
struct phy *mphy;
bool mphy_powered_on;
bool unipro_lpm;
bool ref_clk_enabled;
u16 ref_clk_ungating_wait_us;
u16 ref_clk_gating_wait_us;
};
#endif /* !_UFS_MEDIATEK_H */
|
