From 8d5b5d5ce58ee1b90110f4e358eefe3c3a6b08a2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sun, 1 May 2016 19:36:57 +0900 Subject: reset: add devm_reset_controller_register API Add a device managed API for reset_controller_register(). This helps in reducing code in .remove callbacks and sometimes dropping .remove callbacks entirely. Signed-off-by: Masahiro Yamada Acked-by: Laxman Dewangan Signed-off-by: Philipp Zabel --- Documentation/driver-model/devres.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/driver-model/devres.txt b/Documentation/driver-model/devres.txt index c63eea0c1c8c..f5e522342ee5 100644 --- a/Documentation/driver-model/devres.txt +++ b/Documentation/driver-model/devres.txt @@ -352,6 +352,10 @@ REGULATOR devm_regulator_put() devm_regulator_register() +RESET + devm_reset_control_get() + devm_reset_controller_register() + SLAVE DMA ENGINE devm_acpi_dma_controller_register() -- cgit v1.2.3-58-ga151 From 79795e20a184ebabf4ae743d1506cc39783caa46 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 30 May 2016 15:27:16 +0200 Subject: dt-bindings: reset: Add bindings for the Meson SoC Reset Controller Add DT bindings for the Meson SoC Reset Controller documentation and the associated include file. Acked-by: Rob Herring Signed-off-by: Neil Armstrong Signed-off-by: Philipp Zabel --- .../bindings/reset/amlogic,meson-reset.txt | 18 ++ .../dt-bindings/reset/amlogic,meson-gxbb-reset.h | 210 +++++++++++++++++++++ include/dt-bindings/reset/amlogic,meson8b-reset.h | 175 +++++++++++++++++ 3 files changed, 403 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt create mode 100644 include/dt-bindings/reset/amlogic,meson-gxbb-reset.h create mode 100644 include/dt-bindings/reset/amlogic,meson8b-reset.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt new file mode 100644 index 000000000000..e746b631793a --- /dev/null +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt @@ -0,0 +1,18 @@ +Amlogic Meson SoC Reset Controller +======================================= + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "amlogic,meson8b-reset" or "amlogic,meson-gxbb-reset" +- reg: should contain the register address base +- #reset-cells: 1, see below + +example: + +reset: reset-controller { + compatible = "amlogic,meson-gxbb-reset"; + reg = <0x0 0x04404 0x0 0x20>; + #reset-cells = <1>; +}; diff --git a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h new file mode 100644 index 000000000000..524d6077ac1b --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h @@ -0,0 +1,210 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + * The full GNU General Public License is included in this distribution + * in the file called COPYING. + * + * BSD LICENSE + * + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H + +/* RESET0 */ +#define RESET_HIU 0 +/* 1 */ +#define RESET_DOS_RESET 2 +#define RESET_DDR_TOP 3 +#define RESET_DCU_RESET 4 +#define RESET_VIU 5 +#define RESET_AIU 6 +#define RESET_VID_PLL_DIV 7 +/* 8 */ +#define RESET_PMUX 9 +#define RESET_VENC 10 +#define RESET_ASSIST 11 +#define RESET_AFIFO2 12 +#define RESET_VCBUS 13 +/* 14 */ +/* 15 */ +#define RESET_GIC 16 +#define RESET_CAPB3_DECODE 17 +#define RESET_NAND_CAPB3 18 +#define RESET_HDMITX_CAPB3 19 +#define RESET_MALI_CAPB3 20 +#define RESET_DOS_CAPB3 21 +#define RESET_SYS_CPU_CAPB3 22 +#define RESET_CBUS_CAPB3 23 +#define RESET_AHB_CNTL 24 +#define RESET_AHB_DATA 25 +#define RESET_VCBUS_CLK81 26 +#define RESET_MMC 27 +#define RESET_MIPI_0 28 +#define RESET_MIPI_1 29 +#define RESET_MIPI_2 30 +#define RESET_MIPI_3 31 +/* RESET1 */ +#define RESET_CPPM 32 +#define RESET_DEMUX 33 +#define RESET_USB_OTG 34 +#define RESET_DDR 35 +#define RESET_AO_RESET 36 +#define RESET_BT656 37 +#define RESET_AHB_SRAM 38 +/* 39 */ +#define RESET_PARSER 40 +#define RESET_BLKMV 41 +#define RESET_ISA 42 +#define RESET_ETHERNET 43 +#define RESET_SD_EMMC_A 44 +#define RESET_SD_EMMC_B 45 +#define RESET_SD_EMMC_C 46 +#define RESET_ROM_BOOT 47 +#define RESET_SYS_CPU_0 48 +#define RESET_SYS_CPU_1 49 +#define RESET_SYS_CPU_2 50 +#define RESET_SYS_CPU_3 51 +#define RESET_SYS_CPU_CORE_0 52 +#define RESET_SYS_CPU_CORE_1 53 +#define RESET_SYS_CPU_CORE_2 54 +#define RESET_SYS_CPU_CORE_3 55 +#define RESET_SYS_PLL_DIV 56 +#define RESET_SYS_CPU_AXI 57 +#define RESET_SYS_CPU_L2 58 +#define RESET_SYS_CPU_P 59 +#define RESET_SYS_CPU_MBIST 60 +/* 61 */ +/* 62 */ +/* 63 */ +/* RESET2 */ +#define RESET_VD_RMEM 64 +#define RESET_AUDIN 65 +#define RESET_HDMI_TX 66 +/* 67 */ +/* 68 */ +/* 69 */ +#define RESET_GE2D 70 +#define RESET_PARSER_REG 71 +#define RESET_PARSER_FETCH 72 +#define RESET_PARSER_CTL 73 +#define RESET_PARSER_TOP 74 +/* 75 */ +/* 76 */ +#define RESET_AO_CPU_RESET 77 +#define RESET_MALI 78 +#define RESET_HDMI_SYSTEM_RESET 79 +/* 80-95 */ +/* RESET3 */ +#define RESET_RING_OSCILLATOR 96 +#define RESET_SYS_CPU 97 +#define RESET_EFUSE 98 +#define RESET_SYS_CPU_BVCI 99 +#define RESET_AIFIFO 100 +#define RESET_TVFE 101 +#define RESET_AHB_BRIDGE_CNTL 102 +/* 103 */ +#define RESET_AUDIO_DAC 104 +#define RESET_DEMUX_TOP 105 +#define RESET_DEMUX_DES 106 +#define RESET_DEMUX_S2P_0 107 +#define RESET_DEMUX_S2P_1 108 +#define RESET_DEMUX_RESET_0 109 +#define RESET_DEMUX_RESET_1 110 +#define RESET_DEMUX_RESET_2 111 +/* 112-127 */ +/* RESET4 */ +/* 128 */ +/* 129 */ +/* 130 */ +/* 131 */ +#define RESET_DVIN_RESET 132 +#define RESET_RDMA 133 +#define RESET_VENCI 134 +#define RESET_VENCP 135 +/* 136 */ +#define RESET_VDAC 137 +#define RESET_RTC 138 +/* 139 */ +#define RESET_VDI6 140 +#define RESET_VENCL 141 +#define RESET_I2C_MASTER_2 142 +#define RESET_I2C_MASTER_1 143 +/* 144-159 */ +/* RESET5 */ +/* 160-191 */ +/* RESET6 */ +#define RESET_PERIPHS_GENERAL 192 +#define RESET_PERIPHS_SPICC 193 +#define RESET_PERIPHS_SMART_CARD 194 +#define RESET_PERIPHS_SAR_ADC 195 +#define RESET_PERIPHS_I2C_MASTER_0 196 +#define RESET_SANA 197 +/* 198 */ +#define RESET_PERIPHS_STREAM_INTERFACE 199 +#define RESET_PERIPHS_SDIO 200 +#define RESET_PERIPHS_UART_0 201 +#define RESET_PERIPHS_UART_1_2 202 +#define RESET_PERIPHS_ASYNC_0 203 +#define RESET_PERIPHS_ASYNC_1 204 +#define RESET_PERIPHS_SPI_0 205 +#define RESET_PERIPHS_SDHC 206 +#define RESET_UART_SLIP 207 +/* 208-223 */ +/* RESET7 */ +#define RESET_USB_DDR_0 224 +#define RESET_USB_DDR_1 225 +#define RESET_USB_DDR_2 226 +#define RESET_USB_DDR_3 227 +/* 228 */ +#define RESET_DEVICE_MMC_ARB 229 +/* 230 */ +#define RESET_VID_LOCK 231 +#define RESET_A9_DMC_PIPEL 232 +/* 233-255 */ + +#endif diff --git a/include/dt-bindings/reset/amlogic,meson8b-reset.h b/include/dt-bindings/reset/amlogic,meson8b-reset.h new file mode 100644 index 000000000000..614aff2c7aff --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson8b-reset.h @@ -0,0 +1,175 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + * The full GNU General Public License is included in this distribution + * in the file called COPYING. + * + * BSD LICENSE + * + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H + +/* RESET0 */ +#define RESET_HIU 0 +#define RESET_VLD 1 +#define RESET_IQIDCT 2 +#define RESET_MC 3 +/* 8 */ +#define RESET_VIU 5 +#define RESET_AIU 6 +#define RESET_MCPU 7 +#define RESET_CCPU 8 +#define RESET_PMUX 9 +#define RESET_VENC 10 +#define RESET_ASSIST 11 +#define RESET_AFIFO2 12 +#define RESET_MDEC 13 +#define RESET_VLD_PART 14 +#define RESET_VIFIFO 15 +/* 16-31 */ +/* RESET1 */ +/* 32 */ +#define RESET_DEMUX 33 +#define RESET_USB_OTG 34 +#define RESET_DDR 35 +#define RESET_VDAC_1 36 +#define RESET_BT656 37 +#define RESET_AHB_SRAM 38 +#define RESET_AHB_BRIDGE 39 +#define RESET_PARSER 40 +#define RESET_BLKMV 41 +#define RESET_ISA 42 +#define RESET_ETHERNET 43 +#define RESET_ABUF 44 +#define RESET_AHB_DATA 45 +#define RESET_AHB_CNTL 46 +#define RESET_ROM_BOOT 47 +/* 48-63 */ +/* RESET2 */ +#define RESET_VD_RMEM 64 +#define RESET_AUDIN 65 +#define RESET_DBLK 66 +#define RESET_PIC_DC 66 +#define RESET_PSC 66 +#define RESET_NAND 66 +#define RESET_GE2D 70 +#define RESET_PARSER_REG 71 +#define RESET_PARSER_FETCH 72 +#define RESET_PARSER_CTL 73 +#define RESET_PARSER_TOP 74 +#define RESET_HDMI_APB 75 +#define RESET_AUDIO_APB 76 +#define RESET_MEDIA_CPU 77 +#define RESET_MALI 78 +#define RESET_HDMI_SYSTEM_RESET 79 +/* 80-95 */ +/* RESET3 */ +#define RESET_RING_OSCILLATOR 96 +#define RESET_SYS_CPU_0 97 +#define RESET_EFUSE 98 +#define RESET_SYS_CPU_BVCI 99 +#define RESET_AIFIFO 100 +#define RESET_AUDIO_PLL_MODULATOR 101 +#define RESET_AHB_BRIDGE_CNTL 102 +#define RESET_SYS_CPU_1 103 +#define RESET_AUDIO_DAC 104 +#define RESET_DEMUX_TOP 105 +#define RESET_DEMUX_DES 106 +#define RESET_DEMUX_S2P_0 107 +#define RESET_DEMUX_S2P_1 108 +#define RESET_DEMUX_RESET_0 109 +#define RESET_DEMUX_RESET_1 110 +#define RESET_DEMUX_RESET_2 111 +/* 112-127 */ +/* RESET4 */ +#define RESET_PL310 128 +#define RESET_A5_APB 129 +#define RESET_A5_AXI 130 +#define RESET_A5 131 +#define RESET_DVIN 132 +#define RESET_RDMA 133 +#define RESET_VENCI 134 +#define RESET_VENCP 135 +#define RESET_VENCT 136 +#define RESET_VDAC_4 137 +#define RESET_RTC 138 +#define RESET_A5_DEBUG 139 +#define RESET_VDI6 140 +#define RESET_VENCL 141 +/* 142-159 */ +/* RESET5 */ +#define RESET_DDR_PLL 160 +#define RESET_MISC_PLL 161 +#define RESET_SYS_PLL 162 +#define RESET_HPLL_PLL 163 +#define RESET_AUDIO_PLL 164 +#define RESET_VID2_PLL 165 +/* 166-191 */ +/* RESET6 */ +#define RESET_PERIPHS_GENERAL 192 +#define RESET_PERIPHS_IR_REMOTE 193 +#define RESET_PERIPHS_SMART_CARD 194 +#define RESET_PERIPHS_SAR_ADC 195 +#define RESET_PERIPHS_I2C_MASTER_0 196 +#define RESET_PERIPHS_I2C_MASTER_1 197 +#define RESET_PERIPHS_I2C_SLAVE 198 +#define RESET_PERIPHS_STREAM_INTERFACE 199 +#define RESET_PERIPHS_SDIO 200 +#define RESET_PERIPHS_UART_0 201 +#define RESET_PERIPHS_UART_1 202 +#define RESET_PERIPHS_ASYNC_0 203 +#define RESET_PERIPHS_ASYNC_1 204 +#define RESET_PERIPHS_SPI_0 205 +#define RESET_PERIPHS_SPI_1 206 +#define RESET_PERIPHS_LED_PWM 207 +/* 208-223 */ +/* RESET7 */ +/* 224-255 */ + +#endif -- cgit v1.2.3-58-ga151 From 1fdab21d1d52a85c31f932844242fec5fb81daac Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Mon, 23 May 2016 09:44:55 +0200 Subject: memory: atmel-ebi: add DT bindings documentation The EBI (External Bus Interface) is used to access external peripherals (NOR, SRAM, NAND, and other specific devices like ethernet controllers). Each device is assigned a CS line and an address range and can have its own configuration (timings, access mode, bus width, ...). This driver provides a generic DT binding to configure a device according to its requirements. For specific device controllers (like the NAND one) the SMC timings should be configured by the controller driver through the matrix and smc syscon regmaps. Signed-off-by: Boris Brezillon Acked-by: Rob Herring Signed-off-by: Alexandre Belloni --- .../bindings/memory-controllers/atmel,ebi.txt | 136 +++++++++++++++++++++ 1 file changed, 136 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt new file mode 100644 index 000000000000..9bb5f57e2066 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt @@ -0,0 +1,136 @@ +* Device tree bindings for Atmel EBI + +The External Bus Interface (EBI) controller is a bus where you can connect +asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs). +The EBI provides a glue-less interface to asynchronous memories through the SMC +(Static Memory Controller). + +Required properties: + +- compatible: "atmel,at91sam9260-ebi" + "atmel,at91sam9261-ebi" + "atmel,at91sam9263-ebi0" + "atmel,at91sam9263-ebi1" + "atmel,at91sam9rl-ebi" + "atmel,at91sam9g45-ebi" + "atmel,at91sam9x5-ebi" + "atmel,sama5d3-ebi" + +- reg: Contains offset/length value for EBI memory mapping. + This property might contain several entries if the EBI + memory range is not contiguous + +- #address-cells: Must be 2. + The first cell encodes the CS. + The second cell encode the offset into the CS memory + range. + +- #size-cells: Must be set to 1. + +- ranges: Encodes CS to memory region association. + +- clocks: Clock feeding the EBI controller. + See clock-bindings.txt + +Children device nodes are representing device connected to the EBI bus. + +Required device node properties: + +- reg: Contains the chip-select id, the offset and the length + of the memory region requested by the device. + +EBI bus configuration will be defined directly in the device subnode. + +Optional EBI/SMC properties: + +- atmel,smc-bus-width: width of the asynchronous device's data bus + 8, 16 or 32. + Default to 8 when undefined. + +- atmel,smc-byte-access-type "write" or "select" (see Atmel datasheet). + Default to "select" when undefined. + +- atmel,smc-read-mode "nrd" or "ncs". + Default to "ncs" when undefined. + +- atmel,smc-write-mode "nwe" or "ncs". + Default to "ncs" when undefined. + +- atmel,smc-exnw-mode "disabled", "frozen" or "ready". + Default to "disabled" when undefined. + +- atmel,smc-page-mode enable page mode if present. The provided value + defines the page size (supported values: 4, 8, + 16 and 32). + +- atmel,smc-tdf-mode: "normal" or "optimized". When set to + "optimized" the data float time is optimized + depending on the next device being accessed + (next device setup time is subtracted to the + current device data float time). + Default to "normal" when undefined. + +If at least one atmel,smc- property is defined the following SMC timing +properties become mandatory. In the other hand, if none of the atmel,smc- +properties are specified, we assume that the EBI bus configuration will be +handled by the sub-device driver, and none of those properties should be +defined. + +All the timings are expressed in nanoseconds (see Atmel datasheet for a full +description). + +- atmel,smc-ncs-rd-setup-ns +- atmel,smc-nrd-setup-ns +- atmel,smc-ncs-wr-setup-ns +- atmel,smc-nwe-setup-ns +- atmel,smc-ncs-rd-pulse-ns +- atmel,smc-nrd-pulse-ns +- atmel,smc-ncs-wr-pulse-ns +- atmel,smc-nwe-pulse-ns +- atmel,smc-nwe-cycle-ns +- atmel,smc-nrd-cycle-ns +- atmel,smc-tdf-ns + +Example: + + ebi: ebi@10000000 { + compatible = "atmel,sama5d3-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&hsmc>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x10000000 + 0x40000000 0x30000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x40000000 0x10000000 + 0x2 0x0 0x50000000 0x10000000 + 0x3 0x0 0x60000000 0x10000000>; + clocks = <&mck>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ebi_addr>; + + nor: flash@0,0 { + compatible = "cfi-flash"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x1000000>; + bank-width = <2>; + + atmel,smc-read-mode = "nrd"; + atmel,smc-write-mode = "nwe"; + atmel,smc-bus-width = <16>; + atmel,smc-ncs-rd-setup-ns = <0>; + atmel,smc-ncs-wr-setup-ns = <0>; + atmel,smc-nwe-setup-ns = <8>; + atmel,smc-nrd-setup-ns = <16>; + atmel,smc-ncs-rd-pulse-ns = <84>; + atmel,smc-ncs-wr-pulse-ns = <84>; + atmel,smc-nrd-pulse-ns = <76>; + atmel,smc-nwe-pulse-ns = <76>; + atmel,smc-nrd-cycle-ns = <107>; + atmel,smc-nwe-cycle-ns = <84>; + atmel,smc-tdf-ns = <16>; + }; + }; + -- cgit v1.2.3-58-ga151 From 43752b8d7999ac2ebab85f28dc0c92e248b7b5fa Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Sun, 5 Jun 2016 18:50:50 +0100 Subject: Documentation: add DT bindings for ARM SCPI power domains The System Control Processor (SCP) provides peripheral devices with power domains that can be enabled and disabled viathe System Control and Power Interface (SCPI) Message Protocol. Add bindings to allow probing of these device power domians. Cc: Rob Herring Tested-by: Mathieu Poirier Tested-by: Jon Medhurst Acked-by: Mark Rutland Reviewed-by: Jon Medhurst Reviewed-by: Kevin Hilman Reviewed-by: Ulf Hansson Signed-off-by: Sudeep Holla --- Documentation/devicetree/bindings/arm/arm,scpi.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt index 313dabdc14f9..faa4b44572e3 100644 --- a/Documentation/devicetree/bindings/arm/arm,scpi.txt +++ b/Documentation/devicetree/bindings/arm/arm,scpi.txt @@ -87,10 +87,33 @@ Required properties: implementation for the IDs to use. For Juno R0 and Juno R1 refer to [3]. +Power domain bindings for the power domains based on SCPI Message Protocol +------------------------------------------------------------ + +This binding uses the generic power domain binding[4]. + +PM domain providers +=================== + +Required properties: + - #power-domain-cells : Should be 1. Contains the device or the power + domain ID value used by SCPI commands. + - num-domains: Total number of power domains provided by SCPI. This is + needed as the SCPI message protocol lacks a mechanism to + query this information at runtime. + +PM domain consumers +=================== + +Required properties: + - power-domains : A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle. + [0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [2] Documentation/devicetree/bindings/thermal/thermal.txt [3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html +[4] Documentation/devicetree/bindings/power/power_domain.txt Example: @@ -144,6 +167,12 @@ scpi_protocol: scpi@2e000000 { compatible = "arm,scpi-sensors"; #thermal-sensor-cells = <1>; }; + + scpi_devpd: scpi-power-domains { + compatible = "arm,scpi-power-domains"; + num-domains = <2>; + #power-domain-cells = <1>; + }; }; cpu@0 { @@ -156,6 +185,7 @@ hdlcd@7ff60000 { ... reg = <0 0x7ff60000 0 0x1000>; clocks = <&scpi_clk 4>; + power-domains = <&scpi_devpd 1>; }; thermal-zones { @@ -186,3 +216,7 @@ The thermal-sensors property in the soc_thermal node uses the temperature sensor provided by SCP firmware to setup a thermal zone. The ID "3" is the sensor identifier for the temperature sensor as used by the firmware. + +The num-domains property in scpi-power-domains domain specifies that +SCPI provides 2 power domains. The hdlcd node uses the power domain with +domain ID 1. -- cgit v1.2.3-58-ga151 From 3680a4a97435496ad22cd0fc9f2ba51751cc4e36 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 9 Jun 2016 21:11:22 -0700 Subject: soc: qcom: Update properties for smem state referencing Update the property names to match device tree bindings, the correct values should be qcom,smem-states and qcom,smem-state-names. Also update the #qcom,smem-state-cells for consistency, before we merge any users of these properties. Signed-off-by: Bjorn Andersson Acked-by: Rob Herring Signed-off-by: Andy Gross --- Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt | 4 ++-- Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt | 4 ++-- drivers/soc/qcom/smem_state.c | 12 ++++++------ drivers/soc/qcom/smsm.c | 2 +- 4 files changed, 11 insertions(+), 11 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt index 5cc82b8353d8..af9ca37221ce 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt @@ -68,7 +68,7 @@ important. Value type: Definition: must be 2 - denoting the bit in the entry and IRQ flags -- #qcom,state-cells: +- #qcom,smem-state-cells: Usage: required for outgoing entries Value type: Definition: must be 1 - denoting the bit in the entry @@ -92,7 +92,7 @@ wcnss-smp2p { wcnss_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; - #qcom,state-cells = <1>; + #qcom,smem-state-cells = <1>; }; wcnss_smp2p_in: slave-kernel { diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt index a6634c70850d..2993b5a97dd6 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt @@ -51,7 +51,7 @@ important. Definition: specifies the offset, in words, of the first bit for this entry -- #qcom,state-cells: +- #qcom,smem-state-cells: Usage: required for local entry Value type: Definition: must be 1 - denotes bit number @@ -91,7 +91,7 @@ smsm { apps_smsm: apps@0 { reg = <0>; - #qcom,state-cells = <1>; + #qcom,smem-state-cells = <1>; }; wcnss_smsm: wcnss@7 { diff --git a/drivers/soc/qcom/smem_state.c b/drivers/soc/qcom/smem_state.c index 54261decb369..d5437ca76ed9 100644 --- a/drivers/soc/qcom/smem_state.c +++ b/drivers/soc/qcom/smem_state.c @@ -104,26 +104,26 @@ struct qcom_smem_state *qcom_smem_state_get(struct device *dev, if (con_id) { index = of_property_match_string(dev->of_node, - "qcom,state-names", + "qcom,smem-state-names", con_id); if (index < 0) { - dev_err(dev, "missing qcom,state-names\n"); + dev_err(dev, "missing qcom,smem-state-names\n"); return ERR_PTR(index); } } ret = of_parse_phandle_with_args(dev->of_node, - "qcom,state", - "#qcom,state-cells", + "qcom,smem-states", + "#qcom,smem-state-cells", index, &args); if (ret) { - dev_err(dev, "failed to parse qcom,state property\n"); + dev_err(dev, "failed to parse qcom,smem-states property\n"); return ERR_PTR(ret); } if (args.args_count != 1) { - dev_err(dev, "invalid #qcom,state-cells\n"); + dev_err(dev, "invalid #qcom,smem-state-cells\n"); return ERR_PTR(-EINVAL); } diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c index 6b777af1bc19..d0337b2a71c8 100644 --- a/drivers/soc/qcom/smsm.c +++ b/drivers/soc/qcom/smsm.c @@ -495,7 +495,7 @@ static int qcom_smsm_probe(struct platform_device *pdev) if (!smsm->hosts) return -ENOMEM; - local_node = of_find_node_with_property(pdev->dev.of_node, "#qcom,state-cells"); + local_node = of_find_node_with_property(pdev->dev.of_node, "#qcom,smem-state-cells"); if (!local_node) { dev_err(&pdev->dev, "no state entry\n"); return -EINVAL; -- cgit v1.2.3-58-ga151 From 50f44e894ad06eb8b401308c3cfe5bceaaa26df2 Mon Sep 17 00:00:00 2001 From: Xinliang Liu Date: Mon, 20 Jun 2016 11:50:04 +0800 Subject: reset: hisilicon: Add media reset controller binding Add compatible for media reset controller. Actually, there are two reset controllers in hi6220 SoC: The peripheral reset controller bits are part of sysctrl registers. The media reset controller bits are part of mediactrl registers. So for the compatible part, it should contain "syscon" for both peripheral and media reset controller. Signed-off-by: Xinliang Liu Signed-off-by: Philipp Zabel --- Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt index e0b185a944ba..c25da39df707 100644 --- a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt @@ -8,7 +8,9 @@ The reset controller registers are part of the system-ctl block on hi6220 SoC. Required properties: -- compatible: may be "hisilicon,hi6220-sysctrl" +- compatible: should be one of the following: + - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller. + - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller. - reg: should be register base and length as documented in the datasheet - #reset-cells: 1, see below -- cgit v1.2.3-58-ga151 From a3828519c39aa9c85bae14bad2572d12dc0d1da6 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Mon, 27 Jun 2016 12:12:16 -0500 Subject: Documentation: dt: reset: Add TI syscon reset binding Add TI syscon reset controller binding. This will hook to the reset framework and use syscon/regmap to set reset bits. This allows reset control of individual SoC subsytems and devices with memory-mapped reset registers in a common register memory space. Signed-off-by: Andrew F. Davis Signed-off-by: Suman Anna Acked-by: Rob Herring Signed-off-by: Philipp Zabel --- .../devicetree/bindings/reset/ti-syscon-reset.txt | 91 ++++++++++++++++++++++ include/dt-bindings/reset/ti-syscon.h | 38 +++++++++ 2 files changed, 129 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/ti-syscon-reset.txt create mode 100644 include/dt-bindings/reset/ti-syscon.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt new file mode 100644 index 000000000000..164c7f34c451 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt @@ -0,0 +1,91 @@ +TI SysCon Reset Controller +======================= + +Almost all SoCs have hardware modules that require reset control in addition +to clock and power control for their functionality. The reset control is +typically provided by means of memory-mapped I/O registers. These registers are +sometimes a part of a larger register space region implementing various +functionalities. This register range is best represented as a syscon node to +allow multiple entities to access their relevant registers in the common +register space. + +A SysCon Reset Controller node defines a device that uses a syscon node +and provides reset management functionality for various hardware modules +present on the SoC. + +SysCon Reset Controller Node +============================ +Each of the reset provider/controller nodes should be a child of a syscon +node and have the following properties. + +Required properties: +-------------------- + - compatible : Should be, + "ti,k2e-pscrst" + "ti,k2l-pscrst" + "ti,k2hk-pscrst" + "ti,syscon-reset" + - #reset-cells : Should be 1. Please see the reset consumer node below + for usage details + - ti,reset-bits : Contains the reset control register information + Should contain 7 cells for each reset exposed to + consumers, defined as: + Cell #1 : offset of the reset assert control + register from the syscon register base + Cell #2 : bit position of the reset in the reset + assert control register + Cell #3 : offset of the reset deassert control + register from the syscon register base + Cell #4 : bit position of the reset in the reset + deassert control register + Cell #5 : offset of the reset status register + from the syscon register base + Cell #6 : bit position of the reset in the + reset status register + Cell #7 : Flags used to control reset behavior, + availible flags defined in the DT include + file + +SysCon Reset Consumer Nodes +=========================== +Each of the reset consumer nodes should have the following properties, +in addition to their own properties. + +Required properties: +-------------------- + - resets : A phandle to the reset controller node and an index number + to a reset specifier as defined above. + +Please also refer to Documentation/devicetree/bindings/reset/reset.txt for +common reset controller usage by consumers. + +Example: +-------- +The following example demonstrates a syscon node, the reset controller node +using the syscon node, and a consumer (a DSP device) on the TI Keystone 2 +Edison SoC. + +/ { + soc { + psc: power-sleep-controller@02350000 { + compatible = "syscon", "simple-mfd"; + reg = <0x02350000 0x1000>; + + pscrst: psc-reset { + compatible = "ti,k2e-pscrst", "ti,syscon-reset"; + #reset-cells = <1>; + + ti,reset-bits = < + 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_SET|DEASSERT_CLEAR|STATUS_SET) /* 0: pcrst-dsp0 */ + 0xa40 5 0xa44 3 0 0 (ASSERT_SET|DEASSERT_CLEAR|STATUS_NONE) /* 1: pcrst-example */ + >; + }; + }; + + dsp0: dsp0 { + ... + resets = <&pscrst 0>; + ... + }; + }; +}; diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h new file mode 100644 index 000000000000..884fd91df8e9 --- /dev/null +++ b/include/dt-bindings/reset/ti-syscon.h @@ -0,0 +1,38 @@ +/* + * TI Syscon Reset definitions + * + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__ +#define __DT_BINDINGS_RESET_TI_SYSCON_H__ + +/* + * The reset does not support the feature and corresponding + * values are not valid + */ +#define ASSERT_NONE (1 << 0) +#define DEASSERT_NONE (1 << 1) +#define STATUS_NONE (1 << 2) + +/* When set this function is activated by setting(vs clearing) this bit */ +#define ASSERT_SET (1 << 3) +#define DEASSERT_SET (1 << 4) +#define STATUS_SET (1 << 5) + +/* The following are the inverse of the above and are added for consistency */ +#define ASSERT_CLEAR (0 << 3) +#define DEASSERT_CLEAR (0 << 4) +#define STATUS_CLEAR (0 << 5) + +#endif -- cgit v1.2.3-58-ga151 From a74a198249c473fba092ee549068cea30d54f07e Mon Sep 17 00:00:00 2001 From: Ivaylo Dimitrov Date: Wed, 22 Jun 2016 22:22:18 +0300 Subject: pwm: omap-dmtimer: Allow for setting dmtimer clock source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit OMAP GP timers can have different input clocks that allow different PWM frequencies. However, there is no other way of setting the clock source but through clocks or clock-names properties of the timer itself. This limits PWM functionality to only the frequencies allowed by the particular clock source. Allowing setting the clock source by PWM rather than by timer allows different PWMs to have different ranges by not hard-wiring the clock source to the timer. Signed-off-by: Ivaylo Dimitrov Acked-by: Rob Herring Acked-by: Thierry Reding Acked-by: Pali Rohár Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt | 4 ++++ drivers/pwm/pwm-omap-dmtimer.c | 12 +++++++----- 2 files changed, 11 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt index 5befb538db95..2e53324fb720 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt @@ -9,6 +9,10 @@ Required properties: Optional properties: - ti,prescaler: Should be a value between 0 and 7, see the timers datasheet +- ti,clock-source: Set dmtimer parent clock, values between 0 and 2: + - 0x00 - high-frequency system clock (timer_sys_ck) + - 0x01 - 32-kHz always-on clock (timer_32k_ck) + - 0x02 - external clock (timer_ext_ck, OMAP2 only) Example: pwm9: dmtimer-pwm@9 { diff --git a/drivers/pwm/pwm-omap-dmtimer.c b/drivers/pwm/pwm-omap-dmtimer.c index 3e95090cd7cf..5ad42f33e70c 100644 --- a/drivers/pwm/pwm-omap-dmtimer.c +++ b/drivers/pwm/pwm-omap-dmtimer.c @@ -245,7 +245,7 @@ static int pwm_omap_dmtimer_probe(struct platform_device *pdev) struct pwm_omap_dmtimer_chip *omap; struct pwm_omap_dmtimer_pdata *pdata; pwm_omap_dmtimer *dm_timer; - u32 prescaler; + u32 v; int status; pdata = dev_get_platdata(&pdev->dev); @@ -306,10 +306,12 @@ static int pwm_omap_dmtimer_probe(struct platform_device *pdev) if (pm_runtime_active(&omap->dm_timer_pdev->dev)) omap->pdata->stop(omap->dm_timer); - /* setup dmtimer prescaler */ - if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", - &prescaler)) - omap->pdata->set_prescaler(omap->dm_timer, prescaler); + if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v)) + omap->pdata->set_prescaler(omap->dm_timer, v); + + /* setup dmtimer clock source */ + if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v)) + omap->pdata->set_source(omap->dm_timer, v); omap->chip.dev = &pdev->dev; omap->chip.ops = &pwm_omap_dmtimer_ops; -- cgit v1.2.3-58-ga151 From b5406176989da601736db862643d3d7ee8335815 Mon Sep 17 00:00:00 2001 From: Ivaylo Dimitrov Date: Wed, 22 Jun 2016 22:22:20 +0300 Subject: ir-rx51: add DT support to driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With the upcoming removal of legacy boot, lets add support to one of the last N900 drivers remaining without it. As the driver still uses omap dmtimer, add auxdata as well. Signed-off-by: Ivaylo Dimitrov Acked-by: Rob Herring Acked-by: Pali Rohár Signed-off-by: Tony Lindgren --- .../devicetree/bindings/media/nokia,n900-ir | 20 ++++++++++++++++++++ arch/arm/mach-omap2/pdata-quirks.c | 6 +----- drivers/media/rc/ir-rx51.c | 11 ++++++++++- 3 files changed, 31 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/nokia,n900-ir (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/media/nokia,n900-ir b/Documentation/devicetree/bindings/media/nokia,n900-ir new file mode 100644 index 000000000000..13a18ce37dd1 --- /dev/null +++ b/Documentation/devicetree/bindings/media/nokia,n900-ir @@ -0,0 +1,20 @@ +Device-Tree bindings for LIRC TX driver for Nokia N900(RX51) + +Required properties: + - compatible: should be "nokia,n900-ir". + - pwms: specifies PWM used for IR signal transmission. + +Example node: + + pwm9: dmtimer-pwm@9 { + compatible = "ti,omap-dmtimer-pwm"; + ti,timers = <&timer9>; + ti,clock-source = <0x00>; /* timer_sys_ck */ + #pwm-cells = <3>; + }; + + ir: n900-ir { + compatible = "nokia,n900-ir"; + + pwms = <&pwm9 0 26316 0>; /* 38000 Hz */ + }; diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 278bb8f3b77b..0d7b05a36b99 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -273,8 +273,6 @@ static struct platform_device omap3_rom_rng_device = { }, }; -static struct platform_device rx51_lirc_device; - static void __init nokia_n900_legacy_init(void) { hsmmc2_internal_input_clk(); @@ -293,10 +291,7 @@ static void __init nokia_n900_legacy_init(void) pr_info("RX-51: Registering OMAP3 HWRNG device\n"); platform_device_register(&omap3_rom_rng_device); - } - - platform_device_register(&rx51_lirc_device); } static void __init omap3_tao3530_legacy_init(void) @@ -531,6 +526,7 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { &omap3_iommu_pdata), OF_DEV_AUXDATA("ti,omap3-hsmmc", 0x4809c000, "4809c000.mmc", &mmc_pdata[0]), OF_DEV_AUXDATA("ti,omap3-hsmmc", 0x480b4000, "480b4000.mmc", &mmc_pdata[1]), + OF_DEV_AUXDATA("nokia,n900-ir", 0, "n900-ir", &rx51_lirc_data), /* Only on am3517 */ OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL), OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0", diff --git a/drivers/media/rc/ir-rx51.c b/drivers/media/rc/ir-rx51.c index 5096ef3108d9..1cbb43d0a350 100644 --- a/drivers/media/rc/ir-rx51.c +++ b/drivers/media/rc/ir-rx51.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -478,6 +479,14 @@ static int lirc_rx51_remove(struct platform_device *dev) return lirc_unregister_driver(lirc_rx51_driver.minor); } +static const struct of_device_id lirc_rx51_match[] = { + { + .compatible = "nokia,n900-ir", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, lirc_rx51_match); + struct platform_driver lirc_rx51_platform_driver = { .probe = lirc_rx51_probe, .remove = lirc_rx51_remove, @@ -485,7 +494,7 @@ struct platform_driver lirc_rx51_platform_driver = { .resume = lirc_rx51_resume, .driver = { .name = DRIVER_NAME, - .owner = THIS_MODULE, + .of_match_table = of_match_ptr(lirc_rx51_match), }, }; module_platform_driver(lirc_rx51_platform_driver); -- cgit v1.2.3-58-ga151 From 894b68e1941fa572a97dc059865e5669ecaa3b4a Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 17 Jun 2016 13:40:31 +0100 Subject: dt-bindings: bus: Add documentation for Tegra210 ACONNECT Add binding documentation for the Tegra ACONNECT bus that is part of the Audio Processing Engine (APE) on Tegra210. The ACONNECT bus is used to access devices within the APE subsystem. The APE is located in a separate power domain and so accesses made to the ACONNECT require the power domain to be enabled as well as some platform specific clocks. Signed-off-by: Jon Hunter Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/bus/nvidia,tegra210-aconnect.txt | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt new file mode 100644 index 000000000000..7ff13be1750b --- /dev/null +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt @@ -0,0 +1,45 @@ +NVIDIA Tegra ACONNECT Bus + +The Tegra ACONNECT bus is an AXI switch which is used to connnect various +components inside the Audio Processing Engine (APE). All CPU accesses to +the APE subsystem go through the ACONNECT via an APB to AXI wrapper. + +Required properties: +- compatible: Must be "nvidia,tegra210-aconnect". +- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE), + and APE interface clock (TEGRA210_CLK_APB2APE). +- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding + 'clocks' entries. +- power-domains: Must contain a phandle that points to the audio powergate + (namely 'aud') for Tegra210. +- #address-cells: The number of cells used to represent physical base addresses + in the aconnect address space. Should be 1. +- #size-cells: The number of cells used to represent the size of an address + range in the aconnect address space. Should be 1. +- ranges: Mapping of the aconnect address space to the CPU address space. + +All devices accessed via the ACONNNECT are described by child-nodes. + +Example: + + aconnect@702c0000 { + compatible = "nvidia,tegra210-aconnect"; + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + clock-names = "ape", "apb2ape"; + power-domains = <&pd_audio>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; + + status = "disabled"; + + child1 { + ... + }; + + child2 { + ... + }; + }; -- cgit v1.2.3-58-ga151 From 893b77980c84cfcf2e0caff9740080c351433405 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 4 Jun 2016 10:09:54 +0300 Subject: clk: clps711x: Changing the compatibility string to match with the smallest supported chip This patch changes the compatibility string to match with the smallest supported chip (EP7209). Since the DT-support for this CPU is not yet announced, this change is safe. Signed-off-by: Alexander Shiyan Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/clock/clps711x-clock.txt | 4 ++-- drivers/clk/clk-clps711x.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/clps711x-clock.txt b/Documentation/devicetree/bindings/clock/clps711x-clock.txt index ce5a7476f05d..f1bd53f79d91 100644 --- a/Documentation/devicetree/bindings/clock/clps711x-clock.txt +++ b/Documentation/devicetree/bindings/clock/clps711x-clock.txt @@ -1,7 +1,7 @@ * Clock bindings for the Cirrus Logic CLPS711X CPUs Required properties: -- compatible : Shall contain "cirrus,clps711x-clk". +- compatible : Shall contain "cirrus,ep7209-clk". - reg : Address of the internal register set. - startup-frequency: Factory set CPU startup frequency in HZ. - #clock-cells : Should be <1>. @@ -13,7 +13,7 @@ for the full list of CLPS711X clock IDs. Example: clks: clks@80000000 { #clock-cells = <1>; - compatible = "cirrus,ep7312-clk", "cirrus,clps711x-clk"; + compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk"; reg = <0x80000000 0xc000>; startup-frequency = <73728000>; }; diff --git a/drivers/clk/clk-clps711x.c b/drivers/clk/clk-clps711x.c index 1f60b02416a7..adaf109f2fe2 100644 --- a/drivers/clk/clk-clps711x.c +++ b/drivers/clk/clk-clps711x.c @@ -184,5 +184,5 @@ static void __init clps711x_clk_init_dt(struct device_node *np) of_clk_add_provider(np, of_clk_src_onecell_get, &clps711x_clk->clk_data); } -CLK_OF_DECLARE(clps711x, "cirrus,clps711x-clk", clps711x_clk_init_dt); +CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt); #endif -- cgit v1.2.3-58-ga151 From d64c01058cf769824f71787058aa5211afa81e0d Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 4 Jun 2016 10:09:55 +0300 Subject: clocksource: clps711x: Changing the compatibility string to match with the smallest supported chip This patch changes the compatibility string to match with the smallest supported chip (EP7209). Since the DT-support for this CPU is not yet announced, this change is safe. Signed-off-by: Alexander Shiyan Acked-by: Daniel Lezcano Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt | 6 +++--- drivers/clocksource/clps711x-timer.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt b/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt index cd55b52548e4..d4c62e7b1714 100644 --- a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt +++ b/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt @@ -1,7 +1,7 @@ * Cirrus Logic CLPS711X Timer Counter Required properties: -- compatible: Shall contain "cirrus,clps711x-timer". +- compatible: Shall contain "cirrus,ep7209-timer". - reg : Address and length of the register set. - interrupts: The interrupt number of the timer. - clocks : phandle of timer reference clock. @@ -15,14 +15,14 @@ Example: }; timer1: timer@80000300 { - compatible = "cirrus,ep7312-timer", "cirrus,clps711x-timer"; + compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer"; reg = <0x80000300 0x4>; interrupts = <8>; clocks = <&clks 5>; }; timer2: timer@80000340 { - compatible = "cirrus,ep7312-timer", "cirrus,clps711x-timer"; + compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer"; reg = <0x80000340 0x4>; interrupts = <9>; clocks = <&clks 6>; diff --git a/drivers/clocksource/clps711x-timer.c b/drivers/clocksource/clps711x-timer.c index cdd86e3525bb..7c65f9e1d347 100644 --- a/drivers/clocksource/clps711x-timer.c +++ b/drivers/clocksource/clps711x-timer.c @@ -121,5 +121,5 @@ static void __init clps711x_timer_init(struct device_node *np) break; } } -CLOCKSOURCE_OF_DECLARE(clps711x, "cirrus,clps711x-timer", clps711x_timer_init); +CLOCKSOURCE_OF_DECLARE(clps711x, "cirrus,ep7209-timer", clps711x_timer_init); #endif -- cgit v1.2.3-58-ga151 From 4b4d9949580ef18fd3acc38f1419bca522b5b22e Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 4 Jun 2016 10:09:56 +0300 Subject: irqchip: clps711x: Changing the compatibility string to match with the smallest supported chip This patch changes the compatibility string to match with the smallest supported chip (EP7209). Since the DT-support for this CPU is not yet announced, this change is safe. Signed-off-by: Alexander Shiyan Signed-off-by: Arnd Bergmann --- .../devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt | 4 ++-- drivers/irqchip/irq-clps711x.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt index 759339c34e4f..969b4582ec60 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt @@ -2,7 +2,7 @@ Cirrus Logic CLPS711X Interrupt Controller Required properties: -- compatible: Should be "cirrus,clps711x-intc". +- compatible: Should be "cirrus,ep7209-intc". - reg: Specifies base physical address of the registers set. - interrupt-controller: Identifies the node as an interrupt controller. - #interrupt-cells: Specifies the number of cells needed to encode an @@ -34,7 +34,7 @@ ID Name Description Example: intc: interrupt-controller { - compatible = "cirrus,clps711x-intc"; + compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc"; reg = <0x80000000 0x4000>; interrupt-controller; #interrupt-cells = <1>; diff --git a/drivers/irqchip/irq-clps711x.c b/drivers/irqchip/irq-clps711x.c index 2223b3f15d68..f913f4db7ae1 100644 --- a/drivers/irqchip/irq-clps711x.c +++ b/drivers/irqchip/irq-clps711x.c @@ -234,5 +234,5 @@ static int __init clps711x_intc_init_dt(struct device_node *np, return _clps711x_intc_init(np, res.start, resource_size(&res)); } -IRQCHIP_DECLARE(clps711x, "cirrus,clps711x-intc", clps711x_intc_init_dt); +IRQCHIP_DECLARE(clps711x, "cirrus,ep7209-intc", clps711x_intc_init_dt); #endif -- cgit v1.2.3-58-ga151 From d305345c9dc7360279b6171b74ea3f1913cf53d5 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 4 Jun 2016 10:09:57 +0300 Subject: serial: clps711x: Changing the compatibility string to match with the smallest supported chip This patch changes the compatibility string to match with the smallest supported chip (EP7209). Since the DT-support for this CPU is not yet announced, this change is safe. Signed-off-by: Alexander Shiyan Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt | 4 ++-- drivers/tty/serial/clps711x.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt b/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt index caaeb2583579..07013fa60a48 100644 --- a/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt +++ b/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt @@ -1,7 +1,7 @@ * Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART) Required properties: -- compatible: Should be "cirrus,clps711x-uart". +- compatible: Should be "cirrus,ep7209-uart". - reg: Address and length of the register set for the device. - interrupts: Should contain UART TX and RX interrupt. - clocks: Should contain UART core clock number. @@ -20,7 +20,7 @@ Example: }; uart1: uart@80000480 { - compatible = "cirrus,clps711x-uart"; + compatible = "cirrus,ep7312-uart","cirrus,ep7209-uart"; reg = <0x80000480 0x80>; interrupts = <12 13>; clocks = <&clks 11>; diff --git a/drivers/tty/serial/clps711x.c b/drivers/tty/serial/clps711x.c index 5beafd2d2218..ac1328629baa 100644 --- a/drivers/tty/serial/clps711x.c +++ b/drivers/tty/serial/clps711x.c @@ -539,7 +539,7 @@ static int uart_clps711x_remove(struct platform_device *pdev) } static const struct of_device_id __maybe_unused clps711x_uart_dt_ids[] = { - { .compatible = "cirrus,clps711x-uart", }, + { .compatible = "cirrus,ep7209-uart", }, { } }; MODULE_DEVICE_TABLE(of, clps711x_uart_dt_ids); -- cgit v1.2.3-58-ga151 From ba60ae1dc091b86d4bc74d23c85fc091a632fba7 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 4 Jun 2016 10:09:58 +0300 Subject: pwm: clps711x: Changing the compatibility string to match with the smallest supported chip This patch changes the compatibility string to match with the smallest supported chip (EP7209). Since the DT-support for this CPU is not yet announced, this change is safe. Signed-off-by: Alexander Shiyan Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt | 5 ++--- drivers/pwm/pwm-clps711x.c | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt b/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt index a183db48f910..c0b2028238d6 100644 --- a/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt @@ -1,15 +1,14 @@ * Cirris Logic CLPS711X PWM controller Required properties: -- compatible: Shall contain "cirrus,clps711x-pwm". +- compatible: Shall contain "cirrus,ep7209-pwm". - reg: Physical base address and length of the controller's registers. - clocks: phandle + clock specifier pair of the PWM reference clock. - #pwm-cells: Should be 1. The cell specifies the index of the channel. Example: pwm: pwm@80000400 { - compatible = "cirrus,ep7312-pwm", - "cirrus,clps711x-pwm"; + compatible = "cirrus,ep7312-pwm", "cirrus,ep7209-pwm"; reg = <0x80000400 0x4>; clocks = <&clks 8>; #pwm-cells = <1>; diff --git a/drivers/pwm/pwm-clps711x.c b/drivers/pwm/pwm-clps711x.c index 7d335422cfda..26ec24e457b1 100644 --- a/drivers/pwm/pwm-clps711x.c +++ b/drivers/pwm/pwm-clps711x.c @@ -155,7 +155,7 @@ static int clps711x_pwm_remove(struct platform_device *pdev) } static const struct of_device_id __maybe_unused clps711x_pwm_dt_ids[] = { - { .compatible = "cirrus,clps711x-pwm", }, + { .compatible = "cirrus,ep7209-pwm", }, { } }; MODULE_DEVICE_TABLE(of, clps711x_pwm_dt_ids); -- cgit v1.2.3-58-ga151 From e7c38f221fb256b9ec452531416cca06ebb6d245 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 4 Jun 2016 10:10:01 +0300 Subject: input: clps711x-keypad: Changing the compatibility string to match with the smallest supported chip This patch changes the compatibility string to match with the smallest supported chip (EP7209). Since the DT-support for this CPU is not yet announced, this change is safe. Signed-off-by: Alexander Shiyan Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/input/clps711x-keypad.txt | 4 ++-- drivers/input/keyboard/clps711x-keypad.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/input/clps711x-keypad.txt b/Documentation/devicetree/bindings/input/clps711x-keypad.txt index e68d2bbc6c07..3eed8819d05d 100644 --- a/Documentation/devicetree/bindings/input/clps711x-keypad.txt +++ b/Documentation/devicetree/bindings/input/clps711x-keypad.txt @@ -1,7 +1,7 @@ * Cirrus Logic CLPS711X matrix keypad device tree bindings Required Properties: -- compatible: Shall contain "cirrus,clps711x-keypad". +- compatible: Shall contain "cirrus,ep7209-keypad". - row-gpios: List of GPIOs used as row lines. - poll-interval: Poll interval time in milliseconds. - linux,keymap: The definition can be found at @@ -12,7 +12,7 @@ Optional Properties: Example: keypad { - compatible = "cirrus,ep7312-keypad", "cirrus,clps711x-keypad"; + compatible = "cirrus,ep7312-keypad", "cirrus,ep7209-keypad"; autorepeat; poll-interval = <120>; row-gpios = <&porta 0 0>, diff --git a/drivers/input/keyboard/clps711x-keypad.c b/drivers/input/keyboard/clps711x-keypad.c index b637f1af842e..997e3e97f573 100644 --- a/drivers/input/keyboard/clps711x-keypad.c +++ b/drivers/input/keyboard/clps711x-keypad.c @@ -101,7 +101,7 @@ static int clps711x_keypad_probe(struct platform_device *pdev) return -ENOMEM; priv->syscon = - syscon_regmap_lookup_by_compatible("cirrus,clps711x-syscon1"); + syscon_regmap_lookup_by_compatible("cirrus,ep7209-syscon1"); if (IS_ERR(priv->syscon)) return PTR_ERR(priv->syscon); @@ -181,7 +181,7 @@ static int clps711x_keypad_remove(struct platform_device *pdev) } static const struct of_device_id clps711x_keypad_of_match[] = { - { .compatible = "cirrus,clps711x-keypad", }, + { .compatible = "cirrus,ep7209-keypad", }, { } }; MODULE_DEVICE_TABLE(of, clps711x_keypad_of_match); -- cgit v1.2.3-58-ga151 From 564c9741aa508beba23f3b05b7235775a51bae00 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 4 Jun 2016 10:10:02 +0300 Subject: video: clps711x-fb: Changing the compatibility string to match with the smallest supported chip This patch changes the compatibility string to match with the smallest supported chip (EP7209). Since the DT-support for this CPU is not yet announced, this change is safe. Signed-off-by: Alexander Shiyan Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt | 4 ++-- drivers/video/fbdev/clps711x-fb.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt b/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt index d685be898d0c..e9c65746e2f1 100644 --- a/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt +++ b/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt @@ -1,7 +1,7 @@ * Currus Logic CLPS711X Framebuffer Required properties: -- compatible: Shall contain "cirrus,clps711x-fb". +- compatible: Shall contain "cirrus,ep7209-fb". - reg : Physical base address and length of the controller's registers + location and size of the framebuffer memory. - clocks : phandle + clock specifier pair of the FB reference clock. @@ -18,7 +18,7 @@ Optional properties: Example: fb: fb@800002c0 { - compatible = "cirrus,ep7312-fb", "cirrus,clps711x-fb"; + compatible = "cirrus,ep7312-fb", "cirrus,ep7209-fb"; reg = <0x800002c0 0xd44>, <0x60000000 0xc000>; clocks = <&clks 2>; lcd-supply = <®5v0>; diff --git a/drivers/video/fbdev/clps711x-fb.c b/drivers/video/fbdev/clps711x-fb.c index 649b32f78c08..ff561073ee4e 100644 --- a/drivers/video/fbdev/clps711x-fb.c +++ b/drivers/video/fbdev/clps711x-fb.c @@ -273,7 +273,7 @@ static int clps711x_fb_probe(struct platform_device *pdev) } cfb->syscon = - syscon_regmap_lookup_by_compatible("cirrus,clps711x-syscon1"); + syscon_regmap_lookup_by_compatible("cirrus,ep7209-syscon1"); if (IS_ERR(cfb->syscon)) { ret = PTR_ERR(cfb->syscon); goto out_fb_release; @@ -376,7 +376,7 @@ static int clps711x_fb_remove(struct platform_device *pdev) } static const struct of_device_id clps711x_fb_dt_ids[] = { - { .compatible = "cirrus,clps711x-fb", }, + { .compatible = "cirrus,ep7209-fb", }, { } }; MODULE_DEVICE_TABLE(of, clps711x_fb_dt_ids); -- cgit v1.2.3-58-ga151