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path: root/drivers/phy/cadence
AgeCommit message (Expand)Author
2024-07-02phy: cadence-torrent: Check return value on register readMa Ke
2024-06-03phy: cadence-torrent: add suspend and resume supportThomas Richard
2024-06-03phy: cadence-torrent: remove noop_ops phy operationsThomas Richard
2024-06-03phy: cadence-torrent: add already_configured to struct cdns_torrent_phyThomas Richard
2024-06-03phy: cadence-torrent: register resets even if the phy is already configuredThomas Richard
2024-06-03phy: cadence-torrent: extract calls to clk_get from cdns_torrent_clkThomas Richard
2024-06-03phy: cadence-torrent: Add SGMII + QSGMII multilink configuration for 100MHz r...Swapnil Jakhade
2024-02-07phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink...Swapnil Jakhade
2024-02-07phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink...Swapnil Jakhade
2024-02-07phy: cadence-torrent: Add PCIe(100MHz) + USXGMII(156.25MHz) multilink configu...Swapnil Jakhade
2023-07-17phy: Explicitly include correct DT includesRob Herring
2023-07-12phy: cadence: Sierra: Add single link SGMII register configurationMarcin Wierzbicki
2023-07-12phy: cadence-torrent: Use key:value pair table for all settingsRoger Quadros
2023-07-12phy: cadence-torrent: Add single link USXGMII configuration for 156.25MHz refclkSwapnil Jakhade
2023-07-05Merge tag 'phy-for-6.5_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/p...Linus Torvalds
2023-06-08phy: cadence: torrent: Add a determine_rate hookMaxime Ripard
2023-06-08phy: cadence: sierra: Add a determine_rate hookMaxime Ripard
2023-05-19phy: cadence: salvo: Add cdns,usb2-disconnect-threshold-microvolt propertyFrank Li
2023-05-19phy: cadence: salvo: add .set_mode APIPeter Chen
2023-05-19phy: cadence: salvo: add bist fixPeter Chen
2023-05-19phy: cadence: salvo: decrease delay value to zero for txvalidPeter Chen
2023-05-19phy: cadence: salvo: add access for USB2PHYPeter Chen
2023-05-08phy: cadence-torrent: Add USB + DP multilink configurationSwapnil Jakhade
2023-05-08phy: cadence-torrent: Add PCIe + DP multilink configuration for 100MHz refclkSwapnil Jakhade
2023-05-08phy: cadence-torrent: Prepare driver for multilink DP supportSwapnil Jakhade
2023-05-08phy: cadence-torrent: Add function to get PLL to be configured for DPSwapnil Jakhade
2023-04-12phy: cadence: cdns-dphy-rx: Add common module reset supportSinthu Raja
2023-04-12phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configurationSwapnil Jakhade
2023-03-31phy: cadence: Sierra: Use clk_parent_data to provide parent informationLars-Peter Clausen
2023-03-31phy: cadence: Sierra: Replace `clk_register(`) with `clk_hw_register()`Lars-Peter Clausen
2023-03-20phy: cadence: phy-cadence-torrent: Convert to platform remove callback return...Uwe Kleine-König
2023-03-20phy: cadence: phy-cadence-sierra: Convert to platform remove callback returni...Uwe Kleine-König
2023-03-20phy: cadence: cdns-dphy: Convert to platform remove callback returning voidUwe Kleine-König
2022-07-08phy: cadence-torrent: Remove unused `regmap` field from state structLars-Peter Clausen
2022-07-08phy: cadence: Sierra: Remove unused `regmap` field from state structLars-Peter Clausen
2022-07-05phy: cdns-dphy: Add support for DPHY TX on J721eRahul T R
2022-07-05phy: cdns-dphy: Add band config for dphy txRahul T R
2022-04-13phy: cadence: Sierra: Add TI J721E specific PCIe multilink lane configurationSwapnil Jakhade
2022-03-02phy: cadence: Add Cadence D-PHY Rx driverPratyush Yadav
2022-02-25phy/cadence: Use of_device_get_match_data()Minghao Chi (CGEL ZTE)
2022-02-07phy: cadence: Sierra: Add support for skipping configurationAswath Govindraju
2022-01-24phy: cadence: Sierra: fix error handling bugs in probe()Dan Carpenter
2021-12-27phy: cadence: Sierra: Add support for derived reference clock outputSwapnil Jakhade
2021-12-27phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configurationSwapnil Jakhade
2021-12-27phy: cadence: Sierra: Add support for PHY multilink configurationsSwapnil Jakhade
2021-12-27phy: cadence: Sierra: Fix to get correct parent for mux clocksSwapnil Jakhade
2021-12-27phy: cadence: Sierra: Update single link PCIe register configurationSwapnil Jakhade
2021-12-27phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operationSwapnil Jakhade
2021-12-27phy: cadence: Sierra: Check cmn_ready assertion during PHY power onSwapnil Jakhade
2021-12-27phy: cadence: Sierra: Add PHY PCS common register configurationsSwapnil Jakhade