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2024-09-26Merge tag 'soc-ep93xx-dt-6.12' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC update from Arnd Bergmann: "Convert ep93xx to devicetree This concludes a long journey towards replacing the old board files with devictree description on the Cirrus Logic EP93xx platform. Nikita Shubin has been working on this for a long time, for details see the last post on https://lore.kernel.org/lkml/20240909-ep93xx-v12-0-e86ab2423d4b@maquefel.me/" * tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (47 commits) dt-bindings: gpio: ep9301: Add missing "#interrupt-cells" to examples MAINTAINERS: Update EP93XX ARM ARCHITECTURE maintainer soc: ep93xx: drop reference to removed EP93XX_SOC_COMMON config net: cirrus: use u8 for addr to calm down sparse dmaengine: cirrus: use snprintf() to calm down gcc 13.3.0 dmaengine: ep93xx: Fix a NULL vs IS_ERR() check in probe() pinctrl: ep93xx: Fix raster pins typo spi: ep93xx: update kerneldoc comments for ep93xx_spi clk: ep93xx: Fix off by one in ep93xx_div_recalc_rate() clk: ep93xx: add module license dmaengine: cirrus: remove platform code ASoC: cirrus: edb93xx: Delete driver ARM: ep93xx: soc: drop defines ARM: ep93xx: delete all boardfiles ata: pata_ep93xx: remove legacy pinctrl use pwm: ep93xx: drop legacy pinctrl ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms ARM: dts: ep93xx: Add EDB9302 DT ARM: dts: ep93xx: add ts7250 board ARM: dts: add Cirrus EP93XX SoC .dtsi ...
2024-09-23Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The core clk framework is left largely untouched this time around except for support for the newly ratified DT property 'assigned-clock-rates-u64'. I'm much more excited about the support for loading DT overlays from KUnit tests so that we can test how the clk framework parses DT nodes during clk registration. The clk framework has some places that are highly DeviceTree dependent so this charts the path to extend the KUnit tests to cover even more framework code in the future. I've got some more tests on the list that use the DT overlay support, but they uncovered issues with clk unregistration that I'm still working on fixing. Outside the core, the clk driver update pile is dominated by Qualcomm and Renesas SoCs, making it fairly usual. Looking closer, there are fixes for things all over the place, like adding missing clk frequencies or moving defines for the number of clks out of DT binding headers into the drivers. There are even conversions of DT bindings to YAML and migration away from strings to describe clk topology. Overall it doesn't look unusual so I expect the new drivers to be where we'll have fixes in the coming weeks. Core: - KUnit tests for clk registration and fixed rate basic clk type - A couple more devm helpers, one consumer and one provider - Support for assigned-clock-rates-u64 New Drivers: - Camera, display and GPU clocks on Qualcomm SM4450 - Camera clocks on Qualcomm SM8150 - Rockchip rk3576 clks - Microchip SAM9X7 clks - Renesas RZ/V2H(P) (R9A09G057) clks Updates: - Mark a bunch of struct freq_tbl const to reduce .data usage - Add Qualcomm MSM8226 A7PLL and Regera PLL support - Fix the Qualcomm Lucid 5LPE PLL configuration sequence to not reuse Trion, as they do differ - A number of fixes to the Qualcomm SM8550 display clock driver - Fold Qualcomm SM8650 display clock driver into SM8550 one - Add missing clocks and GDSCs needed for audio on Qualcomm MSM8998 - Add missing USB MP resets, GPLL9, and QUPv3 DFS to Qualcomm SC8180X - Fix sdcc clk frequency tables on Qualcomm SC8180X - Drop the Qualcomm SM8150 gcc_cpuss_ahb_clk_src - Mark Qualcomm PCIe GDSCs as RET_ON on sm8250 and sm8540 to avoid them turning off during suspend - Use the HW_CTRL mechanism on Qualcomm SM8550 video clock controller GDSCs - Get rid of CLK_NR_CLKS defines in Rockchip DT binding headers - Some fixes for Rockchip rk3228 and rk3588 - Exynos850: Add clock for Thermal Management Unit - Exynos7885: Fix duplicated ID in the header, add missing TOP PLLs and add clocks for USB block in the FSYS clock controller - ExynosAutov9: Add DPUM clock controller - ExynosAutov920: Add new (first) clock controllers: TOP and PERIC0 (and a bit more complete bindings) - Use clk_hw pointer instead of fw_name for acm_aud_clk[0-1]_sel clocks on i.MX8Q as parents in ACM provider - Add i.MX95 NETCMIX support to the block control provider - Fix parents for ENETx_REF_SEL clocks on i.MX6UL - Add USB clocks, resets and power domains on Renesas RZ/G3S - Add Generic Timer (GTM), I2C Bus Interface (RIIC), SD/MMC Host Interface (SDHI) and Watchdog Timer (WDT) clocks and resets on Renesas RZ/V2H - Add PCIe, PWM, and CAN-FD clocks on Renesas R-Car V4M - Add LCD controller clocks and resets on Renesas RZ/G2UL - Add DMA clocks and resets on Renesas RZ/G3S - Add fractional multiplication PLL support on Renesas R-Car Gen4 - Document support for the Renesas RZ/G2M v3.0 (r8a774a3) SoC - Support for the Microchip SAM9X7 SoC as follows: - Updates for the Microchip PLL drivers - DT binding documentation updates (for the new clock driver and for the slow clock controller that SAM9X7 is using) - A fix for the Microchip SAMA7G5 clock driver to avoid allocating more memory than necessary - Constify some Amlogic structs - Add SM1 eARC clocks for Amlogic - Introduce a symbol namespace for Amlogic clock specific symbols - Add reset controller support to audiomix block control on i.MX - Add CLK_SET_RATE_PARENT flag to all audiomix clocks and to i.MX7D lcdif_pixel_src clock - Fix parent clocks for earc_phy and audpll on i.MX8MP - Fix default parents for enet[12]_ref_sel on i.MX6UL - Add ops in composite 8M and 93 that allow no-op on disable - Add check for PCC present bit on composite 7ULP register - Fix fractional part for fracn-gppll on prepare in i.MX - Fix clock tree update for TF-A managed clocks on i.MX8M - Drop CLK_SET_PARENT_GATE for DRAM mux on i.MX7D - Add the SAI7 IPG clock for i.MX8MN - Mark the 'nand_usdhc_bus' clock as non-critical on i.MX8MM - Add LVDS bypass clocks on i.MX8QXP - Add muxes for MIPI and PHY ref clocks on i.MX - Reorder dc0_bypass0_clk, lcd_pxl and dc1_disp clocks on i.MX8QXP - Add 1039.5MHz and 800MHz rates to fracn-gppll table on i.MX - Add CLK_SET_RATE_PARENT for media_disp pixel clocks on i.MX8QXP - Add some module descriptions to the i.MX generic and the i.MXRT1050 driver - Fix return value for bypass for composite i.MX7ULP - Move Mediatek clk bindings to clock/ - Convert some more clk bindings to dt schema" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (180 commits) clk: Switch back to struct platform_driver::remove() dt-bindings: clock, reset: fix top-comment indentation rk3576 headers clk: rockchip: remove unused mclk_pdm0_p/pdm0_p definitions clk: provide devm_clk_get_optional_enabled_with_rate() clk: fixed-rate: add devm_clk_hw_register_fixed_rate_parent_data() clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT clk: renesas: rzv2h: Add support for dynamic switching divider clocks clk: renesas: r9a08g045: Add clocks, resets and power domains for USB clk: rockchip: fix error for unknown clocks clk: rockchip: rk3588: drop unused code clk: rockchip: Add clock controller for the RK3576 clk: rockchip: Add new pll type pll_rk3588_ddr dt-bindings: clock, reset: Add support for rk3576 dt-bindings: clock: rockchip,rk3588-cru: drop unneeded assigned-clocks clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p clk: imx95: enable the clock of NETCMIX block control dt-bindings: clock: add RMII clock selection dt-bindings: clock: add i.MX95 NETCMIX block control clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data ...
2024-09-21clk: Switch back to struct platform_driver::remove()Uwe Kleine-König
After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all clk drivers to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/20240909144026.870565-2-u.kleine-koenig@baylibre.com Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-09-21Merge branches 'clk-devm', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into ↵Stephen Boyd
clk-next * clk-devm: clk: provide devm_clk_get_optional_enabled_with_rate() clk: fixed-rate: add devm_clk_hw_register_fixed_rate_parent_data() * clk-samsung: clk: samsung: add top clock support for ExynosAuto v920 SoC clk: samsung: clk-pll: Add support for pll_531x dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings clk: samsung: exynos7885: Add USB related clocks to CMU_FSYS clk: samsung: clk-pll: Add support for pll_1418x clk: samsung: exynosautov9: add dpum clock support dt-bindings: clock: exynosautov9: add dpum clock clk: samsung: exynos7885: Add missing MUX clocks from PLLs in CMU_TOP clk: samsung: exynos7885: Update CLKS_NR_FSYS after bindings fix dt-bindings: clock: exynos7885: Add indices for USB clocks dt-bindings: clock: exynos7885: Add CMU_TOP PLL MUX indices dt-bindings: clock: exynos7885: Fix duplicated binding clk: samsung: exynos850: Add TMU clock dt-bindings: clock: exynos850: Add TMU clock * clk-rockchip: dt-bindings: clock, reset: fix top-comment indentation rk3576 headers clk: rockchip: remove unused mclk_pdm0_p/pdm0_p definitions clk: rockchip: fix error for unknown clocks clk: rockchip: rk3588: drop unused code clk: rockchip: Add clock controller for the RK3576 clk: rockchip: Add new pll type pll_rk3588_ddr dt-bindings: clock, reset: Add support for rk3576 dt-bindings: clock: rockchip,rk3588-cru: drop unneeded assigned-clocks clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p dt-bindings: clock: rockchip: remove CLK_NR_CLKS and CLKPMU_NR_CLKS clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage clk: rockchip: rk3368: Drop CLK_NR_CLKS usage clk: rockchip: rk3328: Drop CLK_NR_CLKS usage clk: rockchip: rk3308: Drop CLK_NR_CLKS usage clk: rockchip: rk3288: Drop CLK_NR_CLKS usage clk: rockchip: rk3228: Drop CLK_NR_CLKS usage clk: rockchip: rk3036: Drop CLK_NR_CLKS usage clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228 * clk-qcom: (47 commits) clk: qcom: videocc-sm8550: Use HW_CTRL_TRIGGER flag for video GDSC's clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLL clk: qcom: dispcc-sm8250: use CLK_SET_RATE_PARENT for branch clocks clk: qcom: ipq5332: Use icc-clk for enabling NoC related clocks clk: qcom: ipq5332: Register gcc_qdss_tsctr_clk_src dt-bindings: usb: qcom,dwc3: Update ipq5332 clock details dt-bindings: interconnect: Add Qualcomm IPQ5332 support clk: qcom: gcc-msm8998: Add Q6 BIMC and LPASS core, ADSP SMMU clocks dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions clk: qcom: Fix SM_CAMCC_8150 dependencies clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src clk: qcom: gcc-sc8180x: Fix the sdcc2 and sdcc4 clocks freq table clk: qcom: gcc-sc8180x: Add GPLL9 support dt-bindings: clock: qcom: Add GPLL9 support on gcc-sc8180x clk: qcom: gcc-sc8180x: Register QUPv3 RCGs for DFS on sc8180x clk: qcom: clk-rpmh: Fix overflow in BCM vote dt-bindings: clock: qcom: Drop required-opps in required on SM8650 camcc dt-bindings: clock: qcom: Drop required-opps in required on sm8650 videocc dt-bindings: clock: qcom,qcs404-turingcc: convert to dtschema dt-bindings: clock: Add x1e80100 LPASSCC reset controller ...
2024-09-21Merge branches 'clk-amlogic', 'clk-microchip' and 'clk-imx' into clk-nextStephen Boyd
* clk-amlogic: clk: meson: introduce symbol namespace for amlogic clocks clk: meson: axg-audio: add sm1 earcrx clocks clk: meson: axg-audio: setup regmap max_register based on the SoC dt-bindings: clock: axg-audio: add earcrx clock ids clk: meson: s4: pll: Constify struct regmap_config clk: meson: s4: peripherals: Constify struct regmap_config clk: meson: c3: pll: Constify struct regmap_config clk: meson: c3: peripherals: Constify struct regmap_config clk: meson: a1: pll: Constify struct regmap_config clk: meson: a1: peripherals: Constify struct regmap_config * clk-microchip: clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs clk: at91: sam9x7: add sam9x7 pmc driver dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT clk: at91: sama7g5: move mux table macros to header file clk: at91: sam9x7: add support for HW PLL freq dividers clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs dt-bindings: clocks: atmel,at91rm9200-pmc: add sam9x7 clock controller dt-bindings: clocks: atmel,at91sam9x5-sckc: add sam9x7 * clk-imx: (27 commits) clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL clk: imx95: enable the clock of NETCMIX block control dt-bindings: clock: add RMII clock selection dt-bindings: clock: add i.MX95 NETCMIX block control clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data clk: imx: composite-7ulp: Use NULL instead of 0 clk: imx: add missing MODULE_DESCRIPTION() macros clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate clk: imx: fracn-gppll: update rate table clk: imx: imx8qxp: Parent should be initialized earlier than the clock clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks clk: imx: imx8qxp: Add LVDS bypass clocks clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one clk: imx: imx8mn: add sai7_ipg_clk clock settings clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D clk: imx: imx8mp: fix clock tree update of TF-A managed clocks clk: imx: fracn-gppll: fix fractional part of PLL getting lost clk: imx: composite-7ulp: Check the PCC present bit ...
2024-09-21Merge branches 'clk-assigned-rates', 'clk-renesas' and 'clk-scmi' into clk-nextStephen Boyd
* clk-assigned-rates: clk: clk-conf: support assigned-clock-rates-u64 * clk-renesas: (34 commits) clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT clk: renesas: rzv2h: Add support for dynamic switching divider clocks clk: renesas: r9a08g045: Add clocks, resets and power domains for USB dt-bindings: clock: renesas,cpg-clocks: Add top-level constraints clk: renesas: r8a779h0: Add CANFD clock clk: renesas: Add RZ/V2H(P) CPG driver clk: renesas: Add family-specific clock driver for RZ/V2H(P) dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG clk: renesas: r8a779h0: Add PWM clock dt-bindings: clock: renesas,cpg-mssr: Document RZ/G2M v3.0 (r8a774a3) clock clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs clk: renesas: rcar-gen4: Remove unused fixed PLL clock types clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs clk: renesas: r8a779a0: Use defines for PLL control registers clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs clk: renesas: rcar-gen4: Add support for fixed variable PLLs clk: renesas: rcar-gen4: Add support for variable fractional PLLs ... * clk-scmi: clk: scmi: add is_prepared hook
2024-09-21Merge branches 'clk-kunit', 'clk-mediatek', 'clk-cleanup' and 'clk-bindings' ↵Stephen Boyd
into clk-next - KUnit tests for clk registration and fixed rate basic clk type * clk-kunit: clk: Add KUnit tests for clks registered with struct clk_parent_data clk: Add KUnit tests for clk fixed rate basic type clk: Add test managed clk provider/consumer APIs platform: Add test managed platform_device/driver APIs of: Add a KUnit test for overlays and test managed APIs dt-bindings: vendor-prefixes: Add "test" vendor for KUnit and friends of: Add test managed wrappers for of_overlay_apply()/of_node_put() of/platform: Allow overlays to create platform devices from the root node * clk-mediatek: dt-bindings: clock: mediatek: Convert MediaTek clock syscons to schema dt-bindings: Move Mediatek clock controllers to "clock" directory dt-bindings: clock: mediatek,apmixedsys: Fix "mediatek,mt6779-apmixed" compatible clk: mediatek: reset: Remove unused mtk_register_reset_controller() clk: mediatek: reset: Return regmap's error code * clk-cleanup: clk: starfive: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage clk: ti: dra7-atl: Fix leak of of_nodes clk:davinci: make use of dev_err_cast_probe() clk: bcm: bcm53573: fix OF node leak in init clk: lmk04832: Use devm_clk_get_enabled() helpers clk: visconti: Switch to use kmemdup_array() clk: mmp: Switch to use kmemdup_array() clk: hisilicon: Remove unnecessary local variable clk: use clk_core_unlink_consumer() helper clk: Use of_property_present() clk: at91: Use of_property_count_u32_elems() to get property length da8xx-cfgchip.c: replace of_node_put with __free improves cleanup * clk-bindings: dt-bindings: clock: st,stm32mp1-rcc: add top-level constraints dt-bindings: clock: cirrus,lochnagar: add top-level constraints dt-bindings: clock: baikal,bt1-ccu-div: add top-level constraints dt-bindings: clock: nxp,lpc3220-usb-clk: Convert bindings to dtschema dt-bindings: clock: nxp,lpc3220-clk: Convert bindings to DT schema
2024-09-12clk: ep93xx: Fix off by one in ep93xx_div_recalc_rate()Dan Carpenter
The psc->div[] array has psc->num_div elements. These values come from when we call clk_hw_register_div(). It's adc_divisors and ARRAY_SIZE(adc_divisors)) and so on. So this condition needs to be >= instead of > to prevent an out of bounds read. Fixes: 9645ccc7bd7a ("ep93xx: clock: convert in-place to COMMON_CLK") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Acked-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Reviewed-by: Nikita Shubin <nikita.shubin@maquefel.me> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Link: https://lore.kernel.org/r/1caf01ad4c0a8069535813c26c7f0b8ea011155e.camel@linaro.org [arnd: the original patch was for arch/arm/mach-ep93xx/clock.c, but the same bug ended up in arch/arm/mach-ep93xx/clock.c. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-09-12clk: ep93xx: add module licenseArnd Bergmann
When configured as a lodable module, this driver produces a build time warning: ERROR: modpost: missing MODULE_LICENSE() in drivers/clk/clk-ep93xx.o All all three tags for license, author and description based on the header. Acked-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-09-12clk: ep93xx: add DT support for Cirrus EP93xxNikita Shubin
Rewrite EP93xx clock driver located in arch/arm/mach-ep93xx/clock.c trying to do everything the device tree way: - provide clock acces via of - drop clk_hw_register_clkdev - drop init code and use module_auxiliary_driver Co-developed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-09-09clk: rockchip: remove unused mclk_pdm0_p/pdm0_p definitionsArnd Bergmann
When -Wunused-const-variable is enabled (not the default), there is a warning about two definitions in this file: In file included from drivers/clk/rockchip/clk-rk3576.c:14: drivers/clk/rockchip/clk-rk3576.c:334:7: error: 'mclk_pdm0_p' defined but not used [-Werror=unused-const-variable=] 334 | PNAME(mclk_pdm0_p) = { "mclk_pdm0_src_top", "xin24m" }; | ^~~~~~~~~~~ drivers/clk/rockchip/clk.h:564:43: note: in definition of macro 'PNAME' 564 | #define PNAME(x) static const char *const x[] __initconst | ^ drivers/clk/rockchip/clk-rk3576.c:333:7: error: 'pdm0_p' defined but not used [-Werror=unused-const-variable=] 333 | PNAME(pdm0_p) = { "clk_pdm0_src_top", "xin24m" }; | ^~~~~~ drivers/clk/rockchip/clk.h:564:43: note: in definition of macro 'PNAME' 564 | #define PNAME(x) static const char *const x[] __initconst | ^ Remove them for the moment. If they are needed later, they can be added back at that point. Fixes: cc40f5baa91b ("clk: rockchip: Add clock controller for the RK3576") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20240909121116.254036-1-arnd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-09-09clk: qcom: clk-alpha-pll: Simplify the zonda_pll_adjust_l_val()Satya Priya Kakitapalli
In zonda_pll_adjust_l_val() replace the divide operator with comparison operator to fix below build error and smatch warning. drivers/clk/qcom/clk-alpha-pll.o: In function `clk_zonda_pll_set_rate': clk-alpha-pll.c:(.text+0x45dc): undefined reference to `__aeabi_uldivmod' smatch warnings: drivers/clk/qcom/clk-alpha-pll.c:2129 zonda_pll_adjust_l_val() warn: replace divide condition '(remainder * 2) / prate' with '(remainder * 2) >= prate' Fixes: f4973130d255 ("clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL") Reported-by: Jon Hunter <jonathanh@nvidia.com> Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/r/202408110724.8pqbpDiD-lkp@intel.com/ Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240906113905.641336-1-quic_skakitap@quicinc.com Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-09-05clk: provide devm_clk_get_optional_enabled_with_rate()Bartosz Golaszewski
There are clock users in the kernel that can't use devm_clk_get_optional_enabled() as they need to set rate after getting the clock and before enabling it. Provide a managed helper that wraps these operations in the correct order. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20240805-clk-new-helper-v2-1-e5fdd1e1d729@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-09-05Merge branch 'clk-imx-old' into clk-imxStephen Boyd
* clk-imx: (22 commits) clk: imx: composite-7ulp: Use NULL instead of 0 clk: imx: add missing MODULE_DESCRIPTION() macros clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate clk: imx: fracn-gppll: update rate table clk: imx: imx8qxp: Parent should be initialized earlier than the clock clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks clk: imx: imx8qxp: Add LVDS bypass clocks clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one clk: imx: imx8mn: add sai7_ipg_clk clock settings clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D clk: imx: imx8mp: fix clock tree update of TF-A managed clocks clk: imx: fracn-gppll: fix fractional part of PLL getting lost clk: imx: composite-7ulp: Check the PCC present bit clk: imx: composite-93: keep root clock on when mcore enabled clk: imx: composite-8m: Enable gate clk with mcore_booted clk: imx: imx6ul: fix default parent for enet*_ref_sel clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpll clk: imx: clk-audiomix: Add CLK_SET_RATE_PARENT flags for clocks ...
2024-09-04clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SELMichel Alex
Commit 4e197ee880c24ecb63f7fe17449b3653bc64b03c ("clk: imx6ul: add ethernet refclock mux support") sets the internal clock as default ethernet clock. Since IMX6UL_CLK_ENET_REF cannot be parent for IMX6UL_CLK_ENET1_REF_SEL, the call to clk_set_parent() fails. IMX6UL_CLK_ENET1_REF_125M is the correct parent and shall be used instead. Same applies for IMX6UL_CLK_ENET2_REF_SEL, for which IMX6UL_CLK_ENET2_REF_125M is the correct parent. Cc: stable@vger.kernel.org Signed-off-by: Alex Michel <alex.michel@wiedemann-group.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.kernel.org/r/AS1P250MB0608F9CE4009DCE65C61EEDEA9922@AS1P250MB0608.EURP250.PROD.OUTLOOK.COM Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-09-03clk: qcom: gcc-sc8280xp: don't use parking clk_ops for QUPsJohan Hovold
A recent change started parking the RCG at an always on parent during registration, something which specifically breaks handover from an early serial console. Quoting Stephen Boyd who fixed this issue for SM8550 [1]: The QUPs aren't shared in a way that requires parking the RCG at an always on parent in case some other entity turns on the clk. The hardware is capable of setting a new frequency itself with the DFS mode, so parking is unnecessary. Furthermore, there aren't any GDSCs for these devices, so there isn't a possibility of the GDSC turning on the clks for housekeeping purposes. This wasn't a problem to mark these clks shared until we started parking shared RCGs at clk registration time in commit 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration"). Parking at init is actually harmful to the UART when earlycon is used. If the device is pumping out data while the frequency changes you'll see garbage on the serial console until the driver can probe and actually set a proper frequency. Fixes: 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration") Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver") Link: https://lore.kernel.org/all/20240819233628.2074654-2-swboyd@chromium.org/ [1] Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20240902070830.8535-1-johan+linaro@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-09-02clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDTLad Prabhakar
Add clock and reset entries for Generic Timer (GTM), I2C Bus Interface (RIIC), SD/MMC Host Interface (SDHI) and Watchdog Timer (WDT) IP blocks. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828093822.162855-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02clk: renesas: rzv2h: Add support for dynamic switching divider clocksLad Prabhakar
Add support for dynamic switching divider clocks. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828093822.162855-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02clk: renesas: r9a08g045: Add clocks, resets and power domains for USBClaudiu Beznea
Add clocks, resets and power domains for USB modules available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240822152801.602318-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-30clk: rockchip: fix error for unknown clocksSebastian Reichel
There is a clk == NULL check after the switch to check for unsupported clk types. Since clk is re-assigned in a loop, this check is useless right now for anything but the first round. Let's fix this up by assigning clk = NULL in the loop before the switch statement. Fixes: a245fecbb806 ("clk: rockchip: add basic infrastructure for clock branches") Cc: stable@vger.kernel.org Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> [added fixes + stable-cc] Link: https://lore.kernel.org/r/20240325193609.237182-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-30clk: rockchip: rk3588: drop unused codeSebastian Reichel
All clocks are registered early using CLK_OF_DECLARE(), which marks the DT node as processed. For the processed DT node the probe routine is never called. Thus this whole code is never executed. This could be "fixed" by using CLK_OF_DECLARE_DRIVER, which avoids marking the DT node as processed. But then the probe routine would re-register all the clocks by calling rk3588_clk_init() again. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240325193609.237182-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-29clk: starfive: jh7110-sys: Add notifier for PLL0 clockXingyu Wu
Add notifier function for PLL0 clock. In the function, the cpu_root clock should be operated by saving its current parent and setting a new safe parent (osc clock) before setting the PLL0 clock rate. After setting PLL0 rate, it should be switched back to the original parent clock. Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") Cc: stable@vger.kernel.org Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20240826080430.179788-2-xingyu.wu@starfivetech.com Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Tested-by: Michael Jeanson <mjeanson@efficios.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-08-29clk: qcom: gcc-sm8650: Don't use shared clk_ops for QUPsNeil Armstrong
The QUPs aren't shared in a way that requires parking the RCG at an always on parent in case some other entity turns on the clk. The hardware is capable of setting a new frequency itself with the DFS mode, so parking is unnecessary. Furthermore, there aren't any GDSCs for these devices, so there isn't a possibility of the GDSC turning on the clks for housekeeping purposes. Like for the SM8550 GCC QUP clocks at [1], do not use shared clk_ops for QUPs. [1] https://lore.kernel.org/all/20240827231237.1014813-3-swboyd@chromium.org/ Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240829-topic-sm8650-upstream-fix-qup-clk-rcg-shared-v1-1-7ecdbc672187@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-08-29clk: qcom: gcc-sm8550: Don't park the USB RCG at registration timeStephen Boyd
Amit Pundir reports that audio and USB-C host mode stops working if the gcc_usb30_prim_master_clk_src clk is registered and clk_rcg2_shared_init() parks it on XO. Skip parking this clk at registration time to fix those issues. Partially revert commit 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration") by skipping the parking bit for this clk, but keep the part where we cache the config register. That's still necessary to figure out the true parent of the clk at registration time. Fixes: 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration") Fixes: 929c75d57566 ("clk: qcom: gcc-sm8550: Mark RCGs shared where applicable") Cc: Konrad Dybcio <konradybcio@kernel.org> Cc: Bjorn Andersson <andersson@kernel.org> Cc: Taniya Das <quic_tdas@quicinc.com> Reported-by: Amit Pundir <amit.pundir@linaro.org> Closes: https://lore.kernel.org/CAMi1Hd1KQBE4kKUdAn8E5FV+BiKzuv+8FoyWQrrTHPDoYTuhgA@mail.gmail.com Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20240819233628.2074654-3-swboyd@chromium.org Tested-by: Amit Pundir <amit.pundir@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-08-29clk: qcom: gcc-sm8550: Don't use parking clk_ops for QUPsStephen Boyd
The QUPs aren't shared in a way that requires parking the RCG at an always on parent in case some other entity turns on the clk. The hardware is capable of setting a new frequency itself with the DFS mode, so parking is unnecessary. Furthermore, there aren't any GDSCs for these devices, so there isn't a possibility of the GDSC turning on the clks for housekeeping purposes. This wasn't a problem to mark these clks shared until we started parking shared RCGs at clk registration time in commit 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration"). Parking at init is actually harmful to the UART when earlycon is used. If the device is pumping out data while the frequency changes you'll see garbage on the serial console until the driver can probe and actually set a proper frequency. Revert the QUP part of commit 929c75d57566 ("clk: qcom: gcc-sm8550: Mark RCGs shared where applicable") so that the QUPs don't get parked during clk registration and break UART operations. Fixes: 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration") Fixes: 929c75d57566 ("clk: qcom: gcc-sm8550: Mark RCGs shared where applicable") Cc: Konrad Dybcio <konradybcio@kernel.org> Cc: Bjorn Andersson <andersson@kernel.org> Cc: Taniya Das <quic_tdas@quicinc.com> Reported-by: Amit Pundir <amit.pundir@linaro.org> Closes: https://lore.kernel.org/CAMi1Hd1KQBE4kKUdAn8E5FV+BiKzuv+8FoyWQrrTHPDoYTuhgA@mail.gmail.com Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20240819233628.2074654-2-swboyd@chromium.org Tested-by: Amit Pundir <amit.pundir@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-08-29clk: rockchip: Add clock controller for the RK3576Elaine Zhang
Add the clock and reset tree definitions for the new RK3576 SoC. As opposed to the other rockchip CRU drivers, the GRF node is looked up via compatible instead of a phandle, which simplifies the device tree bindings. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Reviewed-by: Elaine Zhang <zhangqing@rock-chips.com> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/0102019199a7781a-888440f0-a3f7-4a7d-a831-491260cbdfe7-000000@eu-west-1.amazonses.com [dropped additional blank line at EOF in rst-rk3576.c dropped the whole (non-)working as module part] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-29clk: rockchip: Add new pll type pll_rk3588_ddrElaine Zhang
That PLL type is similar to the other rk3588 pll types but the actual rate is twice the configured rate. Therefore, the returned calculated rate must be multiplied by two. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Acked-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/0102019199a76ec4-9d5846d4-d76a-4e69-a241-c88c2983d607-000000@eu-west-1.amazonses.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-29clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_pAlexander Shiyan
The 32kHz input clock is named "xin32k" in the driver, so the name "32k" appears to be a typo in this case. Lets fix this. Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Fixes: f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Link: https://lore.kernel.org/r/20240829052820.3604-1-eagle.alexander923@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-29clk: imx95: enable the clock of NETCMIX block controlWei Fang
The NETCMIX block control consists of registers for configuration of peripherals in the NETC domain, so enable the clock of NETCMIX to support the configuration. Signed-off-by: Wei Fang <wei.fang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20240829011849.364987-4-wei.fang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-08-29clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_dataShengjiu Wang
"acm_aud_clk0_sel" and "acm_aud_clk1_sel" are registered by this ACM driver, but they are the parent clocks for other clocks, in order to use assigned-clock-parents in device tree, the ".fw_name" can't be used, need to assign the clk_hw pointer for the imx8qm_mclk_sels[], imx8qxp_mclk_sels[], imx8dxl_mclk_sels[]. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/1720600860-18866-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-08-28clk: starfive: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usageYuntao Liu
We need to call pm_runtime_put_noidle() when pm_runtime_get_sync() fails, so use pm_runtime_resume_and_get() instead. this function will handle this. Fixes: dae5448a327ed ("clk: starfive: Add StarFive JH7110 Video-Output clock driver") Signed-off-by: Yuntao Liu <liuyuntao12@huawei.com> Link: https://lore.kernel.org/r/20240815093853.757487-1-liuyuntao12@huawei.com Reviewed-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-08-28clk: ti: dra7-atl: Fix leak of of_nodesDavid Lechner
This fix leaking the of_node references in of_dra7_atl_clk_probe(). The docs for of_parse_phandle_with_args() say that the caller must call of_node_put() on the returned node. This adds the missing of_node_put() to fix the leak. Fixes: 9ac33b0ce81f ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)") Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://lore.kernel.org/r/20240826-clk-fix-leak-v1-1-f55418a13aa6@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-08-28clk:davinci: make use of dev_err_cast_probe()Yuesong Li
Using dev_err_cast_probe() to simplify the code. Signed-off-by: Yuesong Li <liyuesong@vivo.com> Link: https://lore.kernel.org/r/20240828073515.950677-1-liyuesong@vivo.com Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-08-28clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and CLKPMU_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/45f83b1f-64f8-4ea5-bc93-ebf7507a9709@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28clk: rockchip: rk3368: Drop CLK_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/2a19c3cc-5f4d-4d03-90b2-e0bb13b0502f@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28clk: rockchip: rk3328: Drop CLK_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/38ea6be0-3596-49ec-8de9-aef9c7f2bbb6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28clk: rockchip: rk3308: Drop CLK_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/9fbca2d8-f904-4913-ba05-8715e748a454@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28clk: rockchip: rk3288: Drop CLK_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/af141286-7994-4e3f-93e2-6ee4e718ef8a@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28clk: rockchip: rk3228: Drop CLK_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/2ee6f0a5-a1bb-4b62-ae6b-8f3828f8eccc@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28clk: rockchip: rk3036: Drop CLK_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/c8e73847-f472-4473-ac55-068cb28b98f6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and CLKPMU_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/5ad12808-61f5-4e3b-801e-85231375b6a6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28clk: bcm: bcm53573: fix OF node leak in initKrzysztof Kozlowski
Driver code is leaking OF node reference from of_get_parent() in bcm53573_ilp_init(). Usage of of_get_parent() is not needed in the first place, because the parent node will not be freed while we are processing given node (triggered by CLK_OF_DECLARE()). Thus fix the leak by accessing parent directly, instead of of_get_parent(). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240826065801.17081-1-krzysztof.kozlowski@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-08-27clk: lmk04832: Use devm_clk_get_enabled() helpersHuan Yang
The devm_clk_get_enabled() helpers: - call devm_clk_get() - call clk_prepare_enable() and register what is needed in order to call clk_disable_unprepare() when needed, as a managed resource. This simplifies the code and avoids the calls to clk_disable_unprepare(). Signed-off-by: Huan Yang <link@vivo.com> Link: https://lore.kernel.org/r/20240820102119.130298-1-link@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-08-27clk: scmi: add is_prepared hookPeng Fan
Some clocks maybe default enabled by hardware. For clocks that don't have users, that will be left in hardware default state, because prepare count and enable count is zero,if there is no is_prepared hook to get the hardware state. So add is_prepared hook to detect the hardware state. Then when disabling the unused clocks, they can be simply turned OFF to save power during kernel boot. Reviewed-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20240806145601.1184337-1-peng.fan@oss.nxp.com Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-08-27clk: qcom: gcc-x1e80100: Don't use parking clk_ops for QUPsBryan O'Donoghue
Per Stephen Boyd's explanation in the link below, QUP RCG clocks do not need to be parked when switching frequency. A side-effect in parking to a lower frequency can be a momentary invalid clock driven on an in-use serial peripheral. This can cause "junk" to spewed out of a UART as a low-impact example. On the x1e80100-crd this serial port junk can be observed on linux-next. Apply a similar fix to the x1e80100 Global Clock controller to remediate. Link: https://lore.kernel.org/all/20240819233628.2074654-3-swboyd@chromium.org/ Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100") Fixes: 929c75d57566 ("clk: qcom: gcc-sm8550: Mark RCGs shared where applicable") Suggested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20240823-x1e80100-clk-fix-v1-1-0b1b4f5a96e8@linaro.org Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-08-27Merge tag 'qcom-clk-fixes-for-6.11' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-fixes Pull Qualcomm clk driver fixes from Bjorn Andersson: This corrects several issues with the Alpha PLL clock driver. It updates IPQ9574 GCC driver to correctly use the EVO PLL registers for GPLL clocks. X1E USB GDSC flags are corrected to leave these in retention as the controllers are suspended. * tag 'qcom-clk-fixes-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: clk: qcom: ipq9574: Update the alpha PLL type for GPLLs clk: qcom: gcc-x1e80100: Fix USB 0 and 1 PHY GDSC pwrsts flags clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL clk: qcom: clk-alpha-pll: Fix zonda set_rate failure when PLL is disabled clk: qcom: clk-alpha-pll: Fix the trion pll postdiv set rate API clk: qcom: clk-alpha-pll: Fix the pll post div mask
2024-08-24clk: at91: sama7g5: Allocate only the needed amount of memory for PLLsClaudiu Beznea
The maximum number of PLL components on SAMA7G5 is 3 (one fractional part and 2 dividers). Allocate the needed amount of memory for sama7g5_plls 2d array. Previous code used to allocate 7 array entries for each PLL. While at it, replace 3 with PLL_COMPID_MAX in the loop which parses the sama7g5_plls 2d array. Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5") Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240714141315.19480-1-claudiu.beznea@tuxon.dev Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2024-08-23clk: samsung: add top clock support for ExynosAuto v920 SoCSunyeal Hong
This adds support for CMU_TOP which generates clocks for all the function blocks such as CORE, HSI0/1/2, PERIC0/1 and so on. For CMU_TOP, PLL_SHARED0,1,2,3,4 and 5 will be the sources of this block and they will generate bus clocks. Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> Link: https://lore.kernel.org/r/20240821232652.1077701-5-sunyeal.hong@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-23clk: samsung: clk-pll: Add support for pll_531xSunyeal Hong
pll531x PLL is used in Exynos Auto v920 SoC for shared pll. pll531x: Integer/fractional PLL with mid frequency FVCO (800 to 3120 MHz) PLL531x FOUT = (MDIV x FIN)/(PDIV x 2^SDIV) for integer PLL FOUT = (MDIV + F/2^32-F[31]) x FIN/(PDIV x 2^SDIV) for fractional PLL Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20240821232652.1077701-4-sunyeal.hong@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-21clk: samsung: exynos7885: Add USB related clocks to CMU_FSYSDavid Virag
Exynos7885 SoC has a DWC3 USB Controller with Exynos USB PHY which in theory supports USB3 SuperSpeed, but is only used as USB2 in all known devices. These clocks are needed for everything related to USB. While at it, also remove the CLK_SET_RATE_PARENT capability of CLK_MOUT_FSYS_USB30DRD_USER, since it's not actually needed. Signed-off-by: David Virag <virag.david003@gmail.com> Link: https://lore.kernel.org/r/20240816175034.769628-3-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
generated by cgit v1.2.3-58-ga151 (git 2.39.0) at 2024-11-22 13:21:11 +0000