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authorAtish Patra <atish.patra@wdc.com>2022-02-18 16:46:58 -0800
committerPalmer Dabbelt <palmer@rivosinc.com>2022-03-21 15:01:09 -0700
commit4905ec2fb7e6421c14c9fb7276f5aa92f60f2b98 (patch)
treecf945df15c4ac3604682bad5a2247141d6af7ade /include/linux/perf
parente9991434596f5373dfd75857b445eb92a9253c56 (diff)
RISC-V: Add sscofpmf extension support
The sscofpmf extension allows counter overflow and filtering for programmable counters. Enable the perf driver to handle the overflow interrupt. The overflow interrupt is a hart local interrupt. Thus, per cpu overflow interrupts are setup as a child under the root INTC irq domain. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'include/linux/perf')
-rw-r--r--include/linux/perf/riscv_pmu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h
index 0f226948c0ca..46f9b6fe306e 100644
--- a/include/linux/perf/riscv_pmu.h
+++ b/include/linux/perf/riscv_pmu.h
@@ -29,6 +29,8 @@
struct cpu_hw_events {
/* currently enabled events */
int n_events;
+ /* Counter overflow interrupt */
+ int irq;
/* currently enabled events */
struct perf_event *events[RISCV_MAX_COUNTERS];
/* currently enabled hardware counters */