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| author | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2006-03-14 14:18:01 -0600 |
|---|---|---|
| committer | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2006-03-14 14:18:01 -0600 |
| commit | f33b5d783b4f56be5ace6a1c98fb5f76b2d2d07d (patch) | |
| tree | b027b5f3429d416b3da5b9195024007dab062a5e /include/asm-arm/tlbflush.h | |
| parent | e935d5da8e5d12fabe5b632736c50eae0427e8c8 (diff) | |
| parent | 67963132638e67ad3c5aa16765e6f3f2f3cdd85c (diff) | |
Merge ../linux-2.6
Diffstat (limited to 'include/asm-arm/tlbflush.h')
| -rw-r--r-- | include/asm-arm/tlbflush.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h index 9387a5e1ffe0..0c2acc944a0a 100644 --- a/include/asm-arm/tlbflush.h +++ b/include/asm-arm/tlbflush.h @@ -340,6 +340,12 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr)); if (tlb_flag(TLB_V6_I_PAGE)) asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr)); + + /* The ARM ARM states that the completion of a TLB maintenance + * operation is only guaranteed by a DSB instruction + */ + if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE)) + asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero)); } /* |