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authorJuergen Gross <jgross@suse.com>2017-10-27 19:49:37 +0200
committerBoris Ostrovsky <boris.ostrovsky@oracle.com>2017-10-31 09:06:48 -0400
commit6f0e8bf16730a36ff6773802d8c8df56d10e60cd (patch)
tree331fcc02308d71fb979e421a0d4c9508f1cc5e0c /block
parent5eee149ab9f83d1d0eb16c6b32a97d7060eeb490 (diff)
xen: support 52 bit physical addresses in pv guests
Physical addresses on processors supporting 5 level paging can be up to 52 bits wide. For a Xen pv guest running on such a machine those physical addresses have to be supported in order to be able to use any memory on the machine even if the guest itself does not support 5 level paging. So when reading/writing a MFN from/to a pte don't use the kernel's PTE_PFN_MASK but a new XEN_PTE_MFN_MASK allowing full 40 bit wide MFNs. Signed-off-by: Juergen Gross <jgross@suse.com> Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
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