diff options
| author | David Cohen <david.a.cohen@linux.intel.com> | 2013-10-17 15:35:36 -0700 |
|---|---|---|
| committer | H. Peter Anvin <hpa@linux.intel.com> | 2013-10-17 16:41:50 -0700 |
| commit | 40a96d54ee2232045783e657eb9224cd723dcb40 (patch) | |
| tree | 917d337e1b724744cee6ca7610187a821e374a8a /arch/x86/include/asm | |
| parent | 66ac50137049b3d3fab39e5ae245e1562aee5acd (diff) | |
intel_mid: Move platform device setups to their own platform_<device>.* files
As Intel rolling out more SoC's after Moorestown, we need to
re-structure the code in a way that is backward compatible and easy to
expand. This patch implements a flexible way to support multiple boards
and devices.
This patch does not add any new functional support. It just refactors
the existing code to increase the modularity and decrease the code
duplication for supporting multiple soc's and boards.
Currently intel-mid.c has both board and soc related code in one file.
This patch moves the board related code to new files and let linker
script to create SFI devite table following this:
1. Move the SFI device specific code to
arch/x86/platform/intel-mid/device-libs/platform_<device>.*
A new device file is added for every supported device. This code will
get conditionally compiled by using corresponding device driver
CONFIG option.
2. Move the device_ids location to .x86_intel_mid_dev.init section by
using new sfi_device() macro.
This patch was based on previous code from Sathyanarayanan Kuppuswamy.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Link: http://lkml.kernel.org/r/1382049336-21316-13-git-send-email-david.a.cohen@linux.intel.com
Signed-off-by: David Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/x86/include/asm')
| -rw-r--r-- | arch/x86/include/asm/intel-mid.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/x86/include/asm/intel-mid.h b/arch/x86/include/asm/intel-mid.h index 3b0e7a771cb5..459769d39263 100644 --- a/arch/x86/include/asm/intel-mid.h +++ b/arch/x86/include/asm/intel-mid.h @@ -12,8 +12,11 @@ #define _ASM_X86_INTEL_MID_H #include <linux/sfi.h> +#include <linux/platform_device.h> extern int intel_mid_pci_init(void); +extern int get_gpio_by_name(const char *name); +extern void intel_scu_device_register(struct platform_device *pdev); extern int __init sfi_parse_mrtc(struct sfi_table_header *table); extern int __init sfi_parse_mtmr(struct sfi_table_header *table); extern int sfi_mrtc_num; @@ -34,6 +37,10 @@ struct devs_id { struct devs_id *dev); }; +#define sfi_device(i) \ + static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \ + __attribute__((__section__(".x86_intel_mid_dev.init"))) = &i + /* * Medfield is the follow-up of Moorestown, it combines two chip solution into * one. Other than that it also added always-on and constant tsc and lapic @@ -55,9 +62,15 @@ static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void) return __intel_mid_cpu_chip; } +static inline bool intel_mid_has_msic(void) +{ + return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL); +} + #else /* !CONFIG_X86_INTEL_MID */ #define intel_mid_identify_cpu() (0) +#define intel_mid_has_msic() (0) #endif /* !CONFIG_X86_INTEL_MID */ @@ -94,4 +107,7 @@ extern void intel_scu_devices_destroy(void); extern void intel_mid_rtc_init(void); +/* the offset for the mapping of global gpio pin to irq */ +#define INTEL_MID_IRQ_OFFSET 0x100 + #endif /* _ASM_X86_INTEL_MID_H */ |