diff options
| author | Conor Dooley <conor.dooley@microchip.com> | 2023-03-07 21:10:54 +0000 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-03-15 14:43:48 +0000 |
| commit | e77da13b8e3626fc6d01287fba7c1eee4ebfe018 (patch) | |
| tree | 19b73a7bc0867e87629ccb3d90b7be7383b62cf3 /arch/riscv/boot | |
| parent | 0e9b70c1e3623fa110fb6be553e644524228ef60 (diff) | |
riscv: dts: microchip: fix the mpfs' mailbox regs
The mailbox on PolarFire SoC should really have three reg properties,
not two. Without splitting into three sections, the system controller's
QSPI cannot be accessed as it sits inside the current first range. The
driver & binding have been adapted to account for both two & three
ranges, so fix the dts too.
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'arch/riscv/boot')
| -rw-r--r-- | arch/riscv/boot/dts/microchip/mpfs.dtsi | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 23b7b05ee291..104504352e99 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -501,7 +501,8 @@ mbox: mailbox@37020000 { compatible = "microchip,mpfs-mailbox"; - reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; + reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, + <0x0 0x37020800 0x0 0x100>; interrupt-parent = <&plic>; interrupts = <96>; #mbox-cells = <1>; |