diff options
| author | Stafford Horne <shorne@gmail.com> | 2017-07-07 06:06:30 +0900 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2017-11-03 14:01:16 +0900 |
| commit | 4553474d977d1ee8a81067cfbc588f1df84ce3e9 (patch) | |
| tree | 4e74260eb9134fd94a7bc20fc3ab23e4ecb3a7e1 /arch/openrisc/include | |
| parent | 78cdfb5cf15e0f9fb4c2a9176a13a907a1d024f0 (diff) | |
openrisc: add tick timer multi-core sync logic
In case timers are not in sync when cpus start (i.e. hot plug / offset
resets) we need to synchronize the secondary cpus internal timer with
the main cpu. This is needed as in OpenRISC SMP there is only one
clocksource registered which reads from the same ttcr register on each
cpu.
This synchronization routine heavily borrows from mips implementation that
does something similar.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'arch/openrisc/include')
| -rw-r--r-- | arch/openrisc/include/asm/time.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/openrisc/include/asm/time.h b/arch/openrisc/include/asm/time.h index fe83a34a7d68..313ee975774b 100644 --- a/arch/openrisc/include/asm/time.h +++ b/arch/openrisc/include/asm/time.h @@ -12,4 +12,12 @@ extern void openrisc_clockevent_init(void); +extern void openrisc_timer_set(unsigned long count); +extern void openrisc_timer_set_next(unsigned long delta); + +#ifdef CONFIG_SMP +extern void synchronise_count_master(int cpu); +extern void synchronise_count_slave(int cpu); +#endif + #endif /* __ASM_OR1K_TIME_H */ |