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authorHerve Codina <herve.codina@bootlin.com>2023-10-11 08:14:10 +0200
committerRob Herring <robh@kernel.org>2023-10-30 16:28:07 -0500
commitf2147371a83c6de1128093c163dc17bc61096362 (patch)
treee344b0563eda7c156d83a95f829a6f9fb30df666
parent70b416afc99863d9f5a5959f6555bbb290d70eee (diff)
dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Fix example property name
The given example mentions the 'fsl,mode' property whereas the correct property name, the one described, is 'fsl,operational-mode'. Fix the example to use the correct property name. Fixes: a9b121327c93 ("dt-bindings: soc: fsl: cpm_qe: Add QMC controller") Signed-off-by: Herve Codina <herve.codina@bootlin.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231011061437.64213-7-herve.codina@bootlin.com Signed-off-by: Rob Herring <robh@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml6
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
index ec888f48cac8..450a0354cb1d 100644
--- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
@@ -137,7 +137,7 @@ examples:
channel@16 {
/* Ch16 : First 4 even TS from all routed from TSA */
reg = <16>;
- fsl,mode = "transparent";
+ fsl,operational-mode = "transparent";
fsl,reverse-data;
fsl,tx-ts-mask = <0x00000000 0x000000aa>;
fsl,rx-ts-mask = <0x00000000 0x000000aa>;
@@ -146,7 +146,7 @@ examples:
channel@17 {
/* Ch17 : First 4 odd TS from all routed from TSA */
reg = <17>;
- fsl,mode = "transparent";
+ fsl,operational-mode = "transparent";
fsl,reverse-data;
fsl,tx-ts-mask = <0x00000000 0x00000055>;
fsl,rx-ts-mask = <0x00000000 0x00000055>;
@@ -155,7 +155,7 @@ examples:
channel@19 {
/* Ch19 : 8 TS (TS 8..15) from all routed from TSA */
reg = <19>;
- fsl,mode = "hdlc";
+ fsl,operational-mode = "hdlc";
fsl,tx-ts-mask = <0x00000000 0x0000ff00>;
fsl,rx-ts-mask = <0x00000000 0x0000ff00>;
};