1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
|
/*
* Trantor T128/T128F/T228 defines
* Note : architecturally, the T100 and T128 are different and won't work
*
* Copyright 1993, Drew Eckhardt
* Visionary Computing
* (Unix and Linux consulting and custom programming)
* drew@colorado.edu
* +1 (303) 440-4894
*
* For more information, please consult
*
* Trantor Systems, Ltd.
* T128/T128F/T228 SCSI Host Adapter
* Hardware Specifications
*
* Trantor Systems, Ltd.
* 5415 Randall Place
* Fremont, CA 94538
* 1+ (415) 770-1400, FAX 1+ (415) 770-9910
*/
#ifndef T128_H
#define T128_H
/*
* The trantor boards are memory mapped. They use an NCR5380 or
* equivalent (my sample board had part second sourced from ZILOG).
* NCR's recommended "Pseudo-DMA" architecture is used, where
* a PAL drives the DMA signals on the 5380 allowing fast, blind
* transfers with proper handshaking.
*/
/*
* Note : a boot switch is provided for the purpose of informing the
* firmware to boot or not boot from attached SCSI devices. So, I imagine
* there are fewer people who've yanked the ROM like they do on the Seagate
* to make bootup faster, and I'll probably use this for autodetection.
*/
#define T_ROM_OFFSET 0
/*
* Note : my sample board *WAS NOT* populated with the SRAM, so this
* can't be used for autodetection without a ROM present.
*/
#define T_RAM_OFFSET 0x1800
/*
* All of the registers are allocated 32 bytes of address space, except
* for the data register (read/write to/from the 5380 in pseudo-DMA mode)
*/
#define T_CONTROL_REG_OFFSET 0x1c00 /* rw */
#define T_CR_INT 0x10 /* Enable interrupts */
#define T_CR_CT 0x02 /* Reset watchdog timer */
#define T_STATUS_REG_OFFSET 0x1c20 /* ro */
#define T_ST_BOOT 0x80 /* Boot switch */
#define T_ST_S3 0x40 /* User settable switches, */
#define T_ST_S2 0x20 /* read 0 when switch is on, 1 off */
#define T_ST_S1 0x10
#define T_ST_PS2 0x08 /* Set for Microchannel 228 */
#define T_ST_RDY 0x04 /* 5380 DRQ */
#define T_ST_TIM 0x02 /* indicates 40us watchdog timer fired */
#define T_ST_ZERO 0x01 /* Always zero */
#define T_5380_OFFSET 0x1d00 /* 8 registers here, see NCR5380.h */
#define T_DATA_REG_OFFSET 0x1e00 /* rw 512 bytes long */
#ifndef CMD_PER_LUN
#define CMD_PER_LUN 2
#endif
#ifndef CAN_QUEUE
#define CAN_QUEUE 32
#endif
#define NCR5380_implementation_fields \
void __iomem *base
#define NCR5380_local_declare() \
void __iomem *base
#define NCR5380_setup(instance) \
base = ((struct NCR5380_hostdata *)(instance->hostdata))->base
#define T128_address(reg) (base + T_5380_OFFSET + ((reg) * 0x20))
#define NCR5380_read(reg) readb(T128_address(reg))
#define NCR5380_write(reg, value) writeb((value),(T128_address(reg)))
#define NCR5380_intr t128_intr
#define NCR5380_queue_command t128_queue_command
#define NCR5380_abort t128_abort
#define NCR5380_bus_reset t128_bus_reset
#define NCR5380_info t128_info
#define NCR5380_show_info t128_show_info
#define NCR5380_write_info t128_write_info
/* 15 14 12 10 7 5 3
1101 0100 1010 1000 */
#define T128_IRQS 0xc4a8
#endif /* T128_H */
|
