summaryrefslogtreecommitdiff
path: root/arch/csky/mm/tlb.c
blob: 08b8394e5b8f57614770871aed5e51ce731862a3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.

#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/sched.h>

#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/setup.h>

#define CSKY_TLB_SIZE CONFIG_CPU_TLB_SIZE

void flush_tlb_all(void)
{
	tlb_invalid_all();
}

void flush_tlb_mm(struct mm_struct *mm)
{
	int cpu = smp_processor_id();

	if (cpu_context(cpu, mm) != 0)
		drop_mmu_context(mm, cpu);

	tlb_invalid_all();
}

#define restore_asid_inv_utlb(oldpid, newpid) \
do { \
	if ((oldpid & ASID_MASK) == newpid) \
		write_mmu_entryhi(oldpid + 1); \
	write_mmu_entryhi(oldpid); \
} while (0)

void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
			   unsigned long end)
{
	struct mm_struct *mm = vma->vm_mm;
	int cpu = smp_processor_id();

	if (cpu_context(cpu, mm) != 0) {
		unsigned long size, flags;
		int newpid = cpu_asid(cpu, mm);

		local_irq_save(flags);
		size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
		size = (size + 1) >> 1;
		if (size <= CSKY_TLB_SIZE/2) {
			start &= (PAGE_MASK << 1);
			end += ((PAGE_SIZE << 1) - 1);
			end &= (PAGE_MASK << 1);
#ifdef CONFIG_CPU_HAS_TLBI
			while (start < end) {
				asm volatile("tlbi.vaas %0"
					     ::"r"(start | newpid));
				start += (PAGE_SIZE << 1);
			}
			sync_is();
#else
			{
			int oldpid = read_mmu_entryhi();

			while (start < end) {
				int idx;

				write_mmu_entryhi(start | newpid);
				start += (PAGE_SIZE << 1);
				tlb_probe();
				idx = read_mmu_index();
				if (idx >= 0)
					tlb_invalid_indexed();
			}
			restore_asid_inv_utlb(oldpid, newpid);
			}
#endif
		} else {
			drop_mmu_context(mm, cpu);
		}
		local_irq_restore(flags);
	}
}

void flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
	unsigned long size, flags;

	local_irq_save(flags);
	size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
	if (size <= CSKY_TLB_SIZE) {
		start &= (PAGE_MASK << 1);
		end += ((PAGE_SIZE << 1) - 1);
		end &= (PAGE_MASK << 1);
#ifdef CONFIG_CPU_HAS_TLBI
		while (start < end) {
			asm volatile("tlbi.vaas %0"::"r"(start));
			start += (PAGE_SIZE << 1);
		}
		sync_is();
#else
		{
		int oldpid = read_mmu_entryhi();

		while (start < end) {
			int idx;

			write_mmu_entryhi(start);
			start += (PAGE_SIZE << 1);
			tlb_probe();
			idx = read_mmu_index();
			if (idx >= 0)
				tlb_invalid_indexed();
		}
		restore_asid_inv_utlb(oldpid, 0);
		}
#endif
	} else {
		flush_tlb_all();
	}

	local_irq_restore(flags);
}

void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
	int cpu = smp_processor_id();
	int newpid = cpu_asid(cpu, vma->vm_mm);

	if (!vma || cpu_context(cpu, vma->vm_mm) != 0) {
		page &= (PAGE_MASK << 1);

#ifdef CONFIG_CPU_HAS_TLBI
		asm volatile("tlbi.vaas %0"::"r"(page | newpid));
		sync_is();
#else
		{
		int oldpid, idx;
		unsigned long flags;

		local_irq_save(flags);
		oldpid = read_mmu_entryhi();
		write_mmu_entryhi(page | newpid);
		tlb_probe();
		idx = read_mmu_index();
		if (idx >= 0)
			tlb_invalid_indexed();

		restore_asid_inv_utlb(oldpid, newpid);
		local_irq_restore(flags);
		}
#endif
	}
}

/*
 * Remove one kernel space TLB entry.  This entry is assumed to be marked
 * global so we don't do the ASID thing.
 */
void flush_tlb_one(unsigned long page)
{
	int oldpid;

	oldpid = read_mmu_entryhi();
	page &= (PAGE_MASK << 1);

#ifdef CONFIG_CPU_HAS_TLBI
	page = page | (oldpid & 0xfff);
	asm volatile("tlbi.vaas %0"::"r"(page));
	sync_is();
#else
	{
	int idx;
	unsigned long flags;

	page = page | (oldpid & 0xff);

	local_irq_save(flags);
	write_mmu_entryhi(page);
	tlb_probe();
	idx = read_mmu_index();
	if (idx >= 0)
		tlb_invalid_indexed();
	restore_asid_inv_utlb(oldpid, oldpid);
	local_irq_restore(flags);
	}
#endif
}
EXPORT_SYMBOL(flush_tlb_one);

/* show current 32 jtlbs */
void show_jtlb_table(void)
{
	unsigned long flags;
	int entryhi, entrylo0, entrylo1;
	int entry;
	int oldpid;

	local_irq_save(flags);
	entry = 0;
	pr_info("\n\n\n");

	oldpid = read_mmu_entryhi();
	while (entry < CSKY_TLB_SIZE) {
		write_mmu_index(entry);
		tlb_read();
		entryhi = read_mmu_entryhi();
		entrylo0 = read_mmu_entrylo0();
		entrylo0 = entrylo0;
		entrylo1 = read_mmu_entrylo1();
		entrylo1 = entrylo1;
		pr_info("jtlb[%d]:	entryhi - 0x%x;	entrylo0 - 0x%x;"
			"	entrylo1 - 0x%x\n",
			entry, entryhi, entrylo0, entrylo1);
		entry++;
	}
	write_mmu_entryhi(oldpid);
	local_irq_restore(flags);
}