path: root/arch/arm64/boot/dts/st/stm32mp251.dtsi

// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
 */
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/st,stm32mp25-rcc.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a35";
			device_type = "cpu";
			reg = <0>;
			enable-method = "psci";
			power-domains = <&CPU_PD0>;
			power-domain-names = "psci";
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a35-pmu";
		interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>;
		interrupt-parent = <&intc>;
	};

	arm_wdt: watchdog {
		compatible = "arm,smc-wdt";
		arm,smc-id = <0xb200005a>;
		status = "disabled";
	};

	clocks {
		clk_dsi_txbyte: txbyteclk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		clk_rcbsec: clk-rcbsec {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <64000000>;
		};
	};

	firmware {
		optee: optee {
			compatible = "linaro,optee-tz";
			method = "smc";
			interrupt-parent = <&intc>;
			interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
		};

		scmi {
			compatible = "linaro,scmi-optee";
			#address-cells = <1>;
			#size-cells = <0>;
			linaro,optee-channel-id = <0>;

			scmi_clk: protocol@14 {
				reg = <0x14>;
				#clock-cells = <1>;
			};

			scmi_reset: protocol@16 {
				reg = <0x16>;
				#reset-cells = <1>;
			};
		};
	};

	intc: interrupt-controller@4ac00000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		#address-cells = <1>;
		interrupt-controller;
		reg = <0x0 0x4ac10000 0x0 0x1000>,
		      <0x0 0x4ac20000 0x0 0x2000>,
		      <0x0 0x4ac40000 0x0 0x2000>,
		      <0x0 0x4ac60000 0x0 0x2000>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";

		CPU_PD0: power-domain-cpu0 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CLUSTER_PD: power-domain-cluster {
			#power-domain-cells = <0>;
			power-domains = <&RET_PD>;
		};

		RET_PD: power-domain-retention {
			#power-domain-cells = <0>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&intc>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
		always-on;
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges = <0x0 0x0 0x0 0x80000000>;

		rifsc: bus@42080000 {
			compatible = "st,stm32mp25-rifsc", "simple-bus";
			reg = <0x42080000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			#access-controller-cells = <1>;
			ranges;

			spi2: spi@400b0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32mp25-spi";
				reg = <0x400b0000 0x400>;
				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_SPI2>;
				resets = <&rcc SPI2_R>;
				access-controllers = <&rifsc 23>;
				status = "disabled";
			};

			spi3: spi@400c0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32mp25-spi";
				reg = <0x400c0000 0x400>;
				interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_SPI3>;
				resets = <&rcc SPI3_R>;
				access-controllers = <&rifsc 24>;
				status = "disabled";
			};

			usart2: serial@400e0000 {
				compatible = "st,stm32h7-uart";
				reg = <0x400e0000 0x400>;
				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_USART2>;
				access-controllers = <&rifsc 32>;
				status = "disabled";
			};

			usart3: serial@400f0000 {
				compatible = "st,stm32h7-uart";
				reg = <0x400f0000 0x400>;
				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_USART3>;
				access-controllers = <&rifsc 33>;
				status = "disabled";
			};

			uart4: serial@40100000 {
				compatible = "st,stm32h7-uart";
				reg = <0x40100000 0x400>;
				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_UART4>;
				access-controllers = <&rifsc 34>;
				status = "disabled";
			};

			uart5: serial@40110000 {
				compatible = "st,stm32h7-uart";
				reg = <0x40110000 0x400>;
				interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_UART5>;
				access-controllers = <&rifsc 35>;
				status = "disabled";
			};

			i2c1: i2c@40120000 {
				compatible = "st,stm32mp25-i2c";
				reg = <0x40120000 0x400>;
				interrupt-names = "event";
				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_I2C1>;
				resets = <&rcc I2C1_R>;
				#address-cells = <1>;
				#size-cells = <0>;
				access-controllers = <&rifsc 41>;
				status = "disabled";
			};

			i2c2: i2c@40130000 {
				compatible = "st,stm32mp25-i2c";
				reg = <0x40130000 0x400>;
				interrupt-names = "event";
				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_I2C2>;
				resets = <&rcc I2C2_R>;
				#address-cells = <1>;
				#size-cells = <0>;
				access-controllers = <&rifsc 42>;
				status = "disabled";
			};

			i2c3: i2c@40140000 {
				compatible = "st,stm32mp25-i2c";
				reg = <0x40140000 0x400>;
				interrupt-names = "event";
				interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_I2C3>;
				resets = <&rcc I2C3_R>;
				#address-cells = <1>;
				#size-cells = <0>;
				access-controllers = <&rifsc 43>;
				status = "disabled";
			};

			i2c4: i2c@40150000 {
				compatible = "st,stm32mp25-i2c";
				reg = <0x40150000 0x400>;
				interrupt-names = "event";
				interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_I2C4>;
				resets = <&rcc I2C4_R>;
				#address-cells = <1>;
				#size-cells = <0>;
				access-controllers = <&rifsc 44>;
				status = "disabled";
			};

			i2c5: i2c@40160000 {
				compatible = "st,stm32mp25-i2c";
				reg = <0x40160000 0x400>;
				interrupt-names = "event";
				interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_I2C5>;
				resets = <&rcc I2C5_R>;
				#address-cells = <1>;
				#size-cells = <0>;
				access-controllers = <&rifsc 45>;
				status = "disabled";
			};

			i2c6: i2c@40170000 {
				compatible = "st,stm32mp25-i2c";
				reg = <0x40170000 0x400>;
				interrupt-names = "event";
				interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_I2C6>;
				resets = <&rcc I2C6_R>;
				#address-cells = <1>;
				#size-cells = <0>;
				access-controllers = <&rifsc 46>;
				status = "disabled";
			};

			i2c7: i2c@40180000 {
				compatible = "st,stm32mp25-i2c";
				reg = <0x40180000 0x400>;
				interrupt-names = "event";
				interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_I2C7>;
				resets = <&rcc I2C7_R>;
				#address-cells = <1>;
				#size-cells = <0>;
				access-controllers = <&rifsc 47>;
				status = "disabled";
			};

			usart6: serial@40220000 {
				compatible = "st,stm32h7-uart";
				reg = <0x40220000 0x400>;
				interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_USART6>;
				access-controllers = <&rifsc 36>;
				status = "disabled";
			};

			spi1: spi@40230000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32mp25-spi";
				reg = <0x40230000 0x400>;
				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_SPI1>;
				resets = <&rcc SPI1_R>;
				access-controllers = <&rifsc 22>;
				status = "disabled";
			};

			spi4: spi@40240000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32mp25-spi";
				reg = <0x40240000 0x400>;
				interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_SPI4>;
				resets = <&rcc SPI4_R>;
				access-controllers = <&rifsc 25>;
				status = "disabled";
			};

			spi5: spi@40280000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32mp25-spi";
				reg = <0x40280000 0x400>;
				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_SPI5>;
				resets = <&rcc SPI5_R>;
				access-controllers = <&rifsc 26>;
				status = "disabled";
			};

			uart9: serial@402c0000 {
				compatible = "st,stm32h7-uart";
				reg = <0x402c0000 0x400>;
				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_UART9>;
				access-controllers = <&rifsc 39>;
				status = "disabled";
			};

			usart1: serial@40330000 {
				compatible = "st,stm32h7-uart";
				reg = <0x40330000 0x400>;
				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_USART1>;
				access-controllers = <&rifsc 31>;
				status = "disabled";
			};

			spi6: spi@40350000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32mp25-spi";
				reg = <0x40350000 0x400>;
				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_SPI6>;
				resets = <&rcc SPI6_R>;
				access-controllers = <&rifsc 27>;
				status = "disabled";
			};

			spi7: spi@40360000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32mp25-spi";
				reg = <0x40360000 0x400>;
				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_SPI7>;
				resets = <&rcc SPI7_R>;
				access-controllers = <&rifsc 28>;
				status = "disabled";
			};

			uart7: serial@40370000 {
				compatible = "st,stm32h7-uart";
				reg = <0x40370000 0x400>;
				interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_UART7>;
				access-controllers = <&rifsc 37>;
				status = "disabled";
			};

			uart8: serial@40380000 {
				compatible = "st,stm32h7-uart";
				reg = <0x40380000 0x400>;
				interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_UART8>;
				access-controllers = <&rifsc 38>;
				status = "disabled";
			};

			spi8: spi@46020000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32mp25-spi";
				reg = <0x46020000 0x400>;
				interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_SPI8>;
				resets = <&rcc SPI8_R>;
				access-controllers = <&rifsc 29>;
				status = "disabled";
			};

			i2c8: i2c@46040000 {
				compatible = "st,stm32mp25-i2c";
				reg = <0x46040000 0x400>;
				interrupt-names = "event";
				interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_I2C8>;
				resets = <&rcc I2C8_R>;
				#address-cells = <1>;
				#size-cells = <0>;
				access-controllers = <&rifsc 48>;
				status = "disabled";
			};

			sdmmc1: mmc@48220000 {
				compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00353180>;
				reg = <0x48220000 0x400>, <0x44230400 0x8>;
				interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_SDMMC1 >;
				clock-names = "apb_pclk";
				resets = <&rcc SDMMC1_R>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency = <120000000>;
				access-controllers = <&rifsc 76>;
				status = "disabled";
			};
		};

		bsec: efuse@44000000 {
			compatible = "st,stm32mp25-bsec";
			reg = <0x44000000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			part_number_otp@24 {
				reg = <0x24 0x4>;
			};

			package_otp@1e8 {
				reg = <0x1e8 0x1>;
				bits = <0 3>;
			};
		};

		rcc: clock-controller@44200000 {
			compatible = "st,stm32mp25-rcc";
			reg = <0x44200000 0x10000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			clocks = <&scmi_clk CK_SCMI_HSE>,
				<&scmi_clk CK_SCMI_HSI>,
				<&scmi_clk CK_SCMI_MSI>,
				<&scmi_clk CK_SCMI_LSE>,
				<&scmi_clk CK_SCMI_LSI>,
				<&scmi_clk CK_SCMI_HSE_DIV2>,
				<&scmi_clk CK_SCMI_ICN_HS_MCU>,
				<&scmi_clk CK_SCMI_ICN_LS_MCU>,
				<&scmi_clk CK_SCMI_ICN_SDMMC>,
				<&scmi_clk CK_SCMI_ICN_DDR>,
				<&scmi_clk CK_SCMI_ICN_DISPLAY>,
				<&scmi_clk CK_SCMI_ICN_HSL>,
				<&scmi_clk CK_SCMI_ICN_NIC>,
				<&scmi_clk CK_SCMI_ICN_VID>,
				<&scmi_clk CK_SCMI_FLEXGEN_07>,
				<&scmi_clk CK_SCMI_FLEXGEN_08>,
				<&scmi_clk CK_SCMI_FLEXGEN_09>,
				<&scmi_clk CK_SCMI_FLEXGEN_10>,
				<&scmi_clk CK_SCMI_FLEXGEN_11>,
				<&scmi_clk CK_SCMI_FLEXGEN_12>,
				<&scmi_clk CK_SCMI_FLEXGEN_13>,
				<&scmi_clk CK_SCMI_FLEXGEN_14>,
				<&scmi_clk CK_SCMI_FLEXGEN_15>,
				<&scmi_clk CK_SCMI_FLEXGEN_16>,
				<&scmi_clk CK_SCMI_FLEXGEN_17>,
				<&scmi_clk CK_SCMI_FLEXGEN_18>,
				<&scmi_clk CK_SCMI_FLEXGEN_19>,
				<&scmi_clk CK_SCMI_FLEXGEN_20>,
				<&scmi_clk CK_SCMI_FLEXGEN_21>,
				<&scmi_clk CK_SCMI_FLEXGEN_22>,
				<&scmi_clk CK_SCMI_FLEXGEN_23>,
				<&scmi_clk CK_SCMI_FLEXGEN_24>,
				<&scmi_clk CK_SCMI_FLEXGEN_25>,
				<&scmi_clk CK_SCMI_FLEXGEN_26>,
				<&scmi_clk CK_SCMI_FLEXGEN_27>,
				<&scmi_clk CK_SCMI_FLEXGEN_28>,
				<&scmi_clk CK_SCMI_FLEXGEN_29>,
				<&scmi_clk CK_SCMI_FLEXGEN_30>,
				<&scmi_clk CK_SCMI_FLEXGEN_31>,
				<&scmi_clk CK_SCMI_FLEXGEN_32>,
				<&scmi_clk CK_SCMI_FLEXGEN_33>,
				<&scmi_clk CK_SCMI_FLEXGEN_34>,
				<&scmi_clk CK_SCMI_FLEXGEN_35>,
				<&scmi_clk CK_SCMI_FLEXGEN_36>,
				<&scmi_clk CK_SCMI_FLEXGEN_37>,
				<&scmi_clk CK_SCMI_FLEXGEN_38>,
				<&scmi_clk CK_SCMI_FLEXGEN_39>,
				<&scmi_clk CK_SCMI_FLEXGEN_40>,
				<&scmi_clk CK_SCMI_FLEXGEN_41>,
				<&scmi_clk CK_SCMI_FLEXGEN_42>,
				<&scmi_clk CK_SCMI_FLEXGEN_43>,
				<&scmi_clk CK_SCMI_FLEXGEN_44>,
				<&scmi_clk CK_SCMI_FLEXGEN_45>,
				<&scmi_clk CK_SCMI_FLEXGEN_46>,
				<&scmi_clk CK_SCMI_FLEXGEN_47>,
				<&scmi_clk CK_SCMI_FLEXGEN_48>,
				<&scmi_clk CK_SCMI_FLEXGEN_49>,
				<&scmi_clk CK_SCMI_FLEXGEN_50>,
				<&scmi_clk CK_SCMI_FLEXGEN_51>,
				<&scmi_clk CK_SCMI_FLEXGEN_52>,
				<&scmi_clk CK_SCMI_FLEXGEN_53>,
				<&scmi_clk CK_SCMI_FLEXGEN_54>,
				<&scmi_clk CK_SCMI_FLEXGEN_55>,
				<&scmi_clk CK_SCMI_FLEXGEN_56>,
				<&scmi_clk CK_SCMI_FLEXGEN_57>,
				<&scmi_clk CK_SCMI_FLEXGEN_58>,
				<&scmi_clk CK_SCMI_FLEXGEN_59>,
				<&scmi_clk CK_SCMI_FLEXGEN_60>,
				<&scmi_clk CK_SCMI_FLEXGEN_61>,
				<&scmi_clk CK_SCMI_FLEXGEN_62>,
				<&scmi_clk CK_SCMI_FLEXGEN_63>,
				<&scmi_clk CK_SCMI_ICN_APB1>,
				<&scmi_clk CK_SCMI_ICN_APB2>,
				<&scmi_clk CK_SCMI_ICN_APB3>,
				<&scmi_clk CK_SCMI_ICN_APB4>,
				<&scmi_clk CK_SCMI_ICN_APBDBG>,
				<&scmi_clk CK_SCMI_TIMG1>,
				<&scmi_clk CK_SCMI_TIMG2>,
				<&scmi_clk CK_SCMI_PLL3>,
				<&clk_dsi_txbyte>;
				access-controllers = <&rifsc 156>;
		};

		exti1: interrupt-controller@44220000 {
			compatible = "st,stm32mp1-exti", "syscon";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x44220000 0x400>;
			interrupts-extended =
				<&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_0 */
				<&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_10 */
				<&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 1   IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
				<0>,						/* EXTI_20 */
				<&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_30 */
				<&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_40 */
				<&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_50 */
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
				<0>,						/* EXTI_60 */
				<&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<&intc GIC_SPI 10  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_70 */
				<0>,
				<&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
				<0>,						/* EXTI_80 */
				<0>,
				<0>,
				<&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
		};

		syscfg: syscon@44230000 {
			compatible = "st,stm32mp25-syscfg", "syscon";
			reg = <0x44230000 0x10000>;
		};

		pinctrl: pinctrl@44240000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32mp257-pinctrl";
			ranges = <0 0x44240000 0xa0400>;
			interrupt-parent = <&exti1>;
			st,syscfg = <&exti1 0x60 0xff>;
			pins-are-numbered;

			gpioa: gpio@44240000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x0 0x400>;
				clocks = <&scmi_clk CK_SCMI_GPIOA>;
				st,bank-name = "GPIOA";
				status = "disabled";
			};

			gpiob: gpio@44250000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x10000 0x400>;
				clocks = <&scmi_clk CK_SCMI_GPIOB>;
				st,bank-name = "GPIOB";
				status = "disabled";
			};

			gpioc: gpio@44260000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x20000 0x400>;
				clocks = <&scmi_clk CK_SCMI_GPIOC>;
				st,bank-name = "GPIOC";
				status = "disabled";
			};

			gpiod: gpio@44270000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x30000 0x400>;
				clocks = <&scmi_clk CK_SCMI_GPIOD>;
				st,bank-name = "GPIOD";
				status = "disabled";
			};

			gpioe: gpio@44280000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x40000 0x400>;
				clocks = <&scmi_clk CK_SCMI_GPIOE>;
				st,bank-name = "GPIOE";
				status = "disabled";
			};

			gpiof: gpio@44290000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x50000 0x400>;
				clocks = <&scmi_clk CK_SCMI_GPIOF>;
				st,bank-name = "GPIOF";
				status = "disabled";
			};

			gpiog: gpio@442a0000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x60000 0x400>;
				clocks = <&scmi_clk CK_SCMI_GPIOG>;
				st,bank-name = "GPIOG";
				status = "disabled";
			};

			gpioh: gpio@442b0000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x70000 0x400>;
				clocks = <&scmi_clk CK_SCMI_GPIOH>;
				st,bank-name = "GPIOH";
				status = "disabled";
			};

			gpioi: gpio@442c0000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x80000 0x400>;
				clocks = <&scmi_clk CK_SCMI_GPIOI>;
				st,bank-name = "GPIOI";
				status = "disabled";
			};

			gpioj: gpio@442d0000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x90000 0x400>;
				clocks = <&scmi_clk CK_SCMI_GPIOJ>;
				st,bank-name = "GPIOJ";
				status = "disabled";
			};

			gpiok: gpio@442e0000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0xa0000 0x400>;
				clocks = <&scmi_clk CK_SCMI_GPIOK>;
				st,bank-name = "GPIOK";
				status = "disabled";
			};
		};

		pinctrl_z: pinctrl@46200000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32mp257-z-pinctrl";
			ranges = <0 0x46200000 0x400>;
			interrupt-parent = <&exti1>;
			st,syscfg = <&exti1 0x60 0xff>;
			pins-are-numbered;

			gpioz: gpio@46200000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0 0x400>;
				clocks = <&scmi_clk CK_SCMI_GPIOZ>;
				st,bank-name = "GPIOZ";
				st,bank-ioport = <11>;
				status = "disabled";
			};

		};

		exti2: interrupt-controller@46230000 {
			compatible = "st,stm32mp1-exti", "syscon";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x46230000 0x400>;
			interrupts-extended =
				<&intc GIC_SPI 17  IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_0 */
				<&intc GIC_SPI 18  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 19  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 20  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 21  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 22  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 23  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 24  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 25  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 26  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 27  IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_10 */
				<&intc GIC_SPI 28  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 29  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 30  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 31  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 32  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 12  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 13  IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<0>,						/* EXTI_20 */
				<&intc GIC_SPI 14  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 15  IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_30 */
				<&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_40 */
				<0>,
				<0>,
				<&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<&intc GIC_SPI 11  IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<&intc GIC_SPI 5   IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 4   IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 6   IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_50 */
				<&intc GIC_SPI 7   IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 2   IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 3   IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,						/* EXTI_60 */
				<&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;	/* EXTI_70 */
		};
	};
};