blob: 2e1cd219fc182204d4f1c8845701ca757750a0d0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* sc7280 fragment for devices with Chrome bootloader
*
* This file mainly tries to abstract out the memory protections put into
* place by the Chrome bootloader which are different than what's put into
* place by Qualcomm's typical bootloader. It also has a smattering of other
* things that will hold true for any conceivable Chrome design
*
* Copyright 2022 Google LLC.
*/
/*
* Reserved memory changes
*
* Delete all unused memory nodes and define the peripheral memory regions
* required by the setup for Chrome boards.
*/
/delete-node/ &hyp_mem;
/delete-node/ &xbl_mem;
/delete-node/ &reserved_xbl_uefi_log;
/delete-node/ &sec_apps_mem;
/ {
reserved-memory {
adsp_mem: memory@86700000 {
reg = <0x0 0x86700000 0x0 0x2800000>;
no-map;
};
camera_mem: memory@8ad00000 {
reg = <0x0 0x8ad00000 0x0 0x500000>;
no-map;
};
venus_mem: memory@8b200000 {
reg = <0x0 0x8b200000 0x0 0x500000>;
no-map;
};
wpss_mem: memory@9ae00000 {
reg = <0x0 0x9ae00000 0x0 0x1900000>;
no-map;
};
};
};
/* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */
&pmk8350_pon {
status = "disabled";
};
/*
* Chrome designs always boot from SPI flash hooked up to the qspi.
*
* It's expected that all boards will support "dual SPI" at 37.5 MHz.
* If some boards need a different speed or have a package that allows
* Quad SPI together with WP then those boards can easily override.
*/
&qspi {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>;
pinctrl-1 = <&qspi_sleep>;
spi_flash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <37500000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};
};
&remoteproc_wpss {
status = "okay";
firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt";
};
&scm {
/* TF-A firmware maps memory cached so mark dma-coherent to match. */
dma-coherent;
};
&wifi {
status = "okay";
wifi-firmware {
iommus = <&apps_smmu 0x1c02 0x1>;
};
};
/* PINCTRL - chrome-common pinctrl */
&tlmm {
qspi_sleep: qspi-sleep-state {
pins = "gpio12", "gpio13", "gpio14", "gpio15";
/*
* When we're not actively transferring we want pins as GPIOs
* with output disabled so that the quad SPI IP block stops
* driving them. We rely on the normal pulls configured in
* the active state and don't redefine them here. Also note
* that we don't need the reverse (output-enable) in the
* normal mode since the "output-enable" only matters for
* GPIO function.
*/
function = "gpio";
output-disable;
};
};
|
