1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
|
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2023 DH electronics GmbH
*/
#include "imx6ull-dhcor-som.dtsi"
/ {
aliases {
/delete-property/ mmc0; /* Avoid double definitions */
/delete-property/ mmc1;
/delete-property/ spi2;
/delete-property/ spi3;
i2c0 = &i2c2;
i2c1 = &i2c1;
mmc2 = &usdhc2;
rtc0 = &rtc_i2c;
rtc1 = &snvs_rtc;
serial0 = &uart1;
serial1 = &uart6; /* DHCOM UART2, special hardware required */
serial2 = &uart3;
serial3 = &uart2; /* Use BT UART always as ttymxc3 */
serial4 = &uart4;
serial5 = &uart5;
spi0 = &ecspi1;
spi1 = &ecspi4; /* DHCOM SPI2, special hardware required */
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_ext_3v3_ref: regulator-ext-3v3-ref {
compatible = "regulator-fixed";
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VCC_3V3_REF";
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb-otg1-vbus";
};
reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
compatible = "regulator-fixed";
gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb-otg2-vbus";
};
/* SoM with WiFi/BT: WiFi pin WL_REG_ON is connected to a DHCOM GPIO */
/omit-if-no-ref/ usdhc1_pwrseq: usdhc1-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; /* GPIO H */
};
};
/* SoM with WiFi/BT: BT pin BT_REG_ON is connected to a DHCOM GPIO */
&bluetooth {
shutdown-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */
};
&can1 {
pinctrl-0 = <&pinctrl_flexcan1>;
pinctrl-names = "default";
status = "okay";
};
/*
* The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins.
* Only if this pins are used as CAN interface enable it on board layer.
*/
&can2 {
pinctrl-0 = <&pinctrl_flexcan2>;
pinctrl-names = "default";
};
/* DHCOM SPI1 */
&ecspi1 {
cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_ecspi1>;
pinctrl-names = "default";
status = "okay";
};
/*
* DHCOM SPI2
* Special hardware required that uses the pins of FEC2. Therefore this SPI
* interface can only be used if FEC2 is disabled.
*/
&ecspi4 {
cs-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_ecspi4>;
pinctrl-names = "default";
};
/* DHCOM ETH1 */
&fec1 {
phy-handle = <&mdio2_phy0>;
phy-mode = "rmii";
pinctrl-0 = <&pinctrl_fec1>;
pinctrl-names = "default";
status = "okay";
};
/* DHCOM ETH2 */
&fec2 {
phy-handle = <&mdio2_phy1>;
phy-mode = "rmii";
pinctrl-0 = <&pinctrl_fec2>;
pinctrl-names = "default";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
mdio2_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */
"ethernet-phy-ieee802.3-c22";
reg = <0>;
clock-names = "rmii-ref";
clocks = <&clks IMX6UL_CLK_ENET_REF>;
interrupt-parent = <&gpio5>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_fec1_phy &pinctrl_snvs_fec1_phy>;
pinctrl-names = "default";
reset-assert-us = <500>;
reset-deassert-us = <500>;
reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
smsc,disable-energy-detect; /* Make plugin detection reliable */
};
mdio2_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */
"ethernet-phy-ieee802.3-c22";
reg = <1>;
clock-names = "rmii-ref";
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
interrupt-parent = <&gpio5>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_fec2_phy &pinctrl_snvs_fec2_phy>;
pinctrl-names = "default";
reset-assert-us = <500>;
reset-deassert-us = <500>;
reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
smsc,disable-energy-detect; /* Make plugin detection reliable */
};
};
};
&gpio1 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "DHCOM-INT",
"", "", "", "",
"", "", "DHCOM-I", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
pinctrl-0 = <&pinctrl_spi1_switch
&pinctrl_dhcom_i &pinctrl_dhcom_int>;
pinctrl-names = "default";
};
&gpio4 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "DHCOM-L", "DHCOM-K", "DHCOM-M",
"DHCOM-J", "DHCOM-U", "DHCOM-T", "DHCOM-S",
"DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O",
"DHCOM-N", "", "", "";
pinctrl-0 = <&pinctrl_dhcom_j &pinctrl_dhcom_k
&pinctrl_dhcom_l &pinctrl_dhcom_m
&pinctrl_dhcom_n &pinctrl_dhcom_o
&pinctrl_dhcom_p &pinctrl_dhcom_q
&pinctrl_dhcom_r &pinctrl_dhcom_s
&pinctrl_dhcom_t &pinctrl_dhcom_u>;
pinctrl-names = "default";
};
&gpio5 {
gpio-line-names =
"DHCOM-A", "DHCOM-B", "DHCOM-C", "DHCOM-D",
"DHCOM-E", "", "", "DHCOM-F",
"DHCOM-G", "DHCOM-H", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
pinctrl-0 = <&pinctrl_snvs_dhcom_a &pinctrl_snvs_dhcom_b
&pinctrl_snvs_dhcom_c &pinctrl_snvs_dhcom_d
&pinctrl_snvs_dhcom_e &pinctrl_snvs_dhcom_f
&pinctrl_snvs_dhcom_g &pinctrl_snvs_dhcom_h>;
pinctrl-names = "default";
};
/* DHCOM I2C2 */
&i2c1 {
rtc_i2c: rtc@32 {
compatible = "microcrystal,rv8803";
reg = <0x32>;
};
/* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH1 */
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
/* TI ADC101C027 */
adc@51 {
compatible = "ti,adc101c";
reg = <0x51>;
vref-supply = <®_ext_3v3_ref>;
};
/* TI ADC101C027 */
adc@52 {
compatible = "ti,adc101c";
reg = <0x52>;
vref-supply = <®_ext_3v3_ref>;
};
/* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH2 */
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
};
/* DHCOM I2C1 */
&i2c2 {
clock-frequency = <100000>;
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
pinctrl-names = "default", "gpio";
scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&lcdif {
pinctrl-0 = <&pinctrl_lcdif>;
pinctrl-names = "default";
};
&pwm1 {
pinctrl-0 = <&pinctrl_pwm1>;
pinctrl-names = "default";
};
&sai2 {
assigned-clock-rates = <320000000>;
assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>;
pinctrl-0 = <&pinctrl_sai2>;
pinctrl-names = "default";
};
&tsc {
measure-delay-time = <0xffff>;
pinctrl-0 = <&pinctrl_tsc>;
pinctrl-names = "default";
pre-charge-time = <0xfff>;
touchscreen-average-samples = <32>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
};
/* DHCOM UART1 */
&uart1 {
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
status = "okay";
};
/*
* DHCOM UART2 (alternative)
* Special hardware required that uses DHCOM GPIO pins for DHCOM UART2.
* Therefore this UART interface can only be used if DHCOM GPIOs J/K/L/M are
* removed from GPIO hog muxing.
*/
&uart6 {
pinctrl-0 = <&pinctrl_uart6>;
pinctrl-names = "default";
uart-has-rtscts;
};
&usbotg1 {
adp-disable;
disable-over-current;
dr_mode = "otg";
hnp-disable;
pinctrl-0 = <&pinctrl_usbotg1>;
pinctrl-names = "default";
srp-disable;
vbus-supply = <®_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
disable-over-current; /* Overcurrent pin is used for TSC */
dr_mode = "host";
pinctrl-0 = <&pinctrl_usbotg2>;
pinctrl-names = "default";
tpl-support;
vbus-supply = <®_usb_otg2_vbus>;
status = "okay";
};
&usbphy1 {
fsl,tx-d-cal = <106>;
};
&usbphy2 {
fsl,tx-d-cal = <106>;
};
/* WiFi on LGA */
&usdhc1 {
mmc-pwrseq = <&usdhc1_pwrseq>;
};
/* eMMC on module */
&usdhc2 {
bus-width = <8>;
no-1-8-v;
non-removable;
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-names = "default";
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_3v3>;
status = "okay";
};
&iomuxc {
/* DHCOM GPIOs I..U + INT_HIGHEST_PRIORITY */
pinctrl_dhcom_i: dhcom-i-grp {
fsl,pins = <MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x400120b0>;
};
pinctrl_dhcom_j: dhcom-j-grp {
fsl,pins = <MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x400120b0>;
};
pinctrl_dhcom_k: dhcom-k-grp {
fsl,pins = <MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x400120b0>;
};
pinctrl_dhcom_l: dhcom-l-grp {
fsl,pins = <MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x400120b0>;
};
pinctrl_dhcom_m: dhcom-m-grp {
fsl,pins = <MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x400120b0>;
};
pinctrl_dhcom_n: dhcom-n-grp {
fsl,pins = <MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x400120b0>;
};
pinctrl_dhcom_o: dhcom-o-grp {
fsl,pins = <MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x400120b0>;
};
pinctrl_dhcom_p: dhcom-p-grp {
fsl,pins = <MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x400120b0>;
};
pinctrl_dhcom_q: dhcom-q-grp {
fsl,pins = <MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x400120b0>;
};
pinctrl_dhcom_r: dhcom-r-grp {
fsl,pins = <MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x400120b0>;
};
pinctrl_dhcom_s: dhcom-s-grp {
fsl,pins = <MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x400120b0>;
};
pinctrl_dhcom_t: dhcom-t-grp {
fsl,pins = <MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x400120b0>;
};
pinctrl_dhcom_u: dhcom-u-grp {
fsl,pins = <MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x400120b0>;
};
pinctrl_dhcom_int: dhcom-int-grp {
fsl,pins = <MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x400120b0>;
};
pinctrl_ecspi1: ecspi1-grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1
MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1
MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1
MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x1b0b0 /* SS0 */
>;
};
pinctrl_ecspi4: ecspi4-grp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x100b1
MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x100b1
MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x100b1
MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* SS0 */
>;
};
pinctrl_fec1: fec1-grp {
fsl,pins = <
/* FEC1 uses MDIO bus from FEC2 */
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010
>;
};
pinctrl_fec1_phy: fec1-phy-grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0xb0 /* SMSC PHY reset */
>;
};
pinctrl_fec2: fec2-grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
>;
};
pinctrl_fec2_phy: fec2-phy-grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0xb0 /* SMSC PHY reset */
>;
};
pinctrl_flexcan1: flexcan1-grp {
fsl,pins = <
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
>;
};
pinctrl_flexcan2: flexcan2-grp {
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_i2c2: i2c2-grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
>;
};
pinctrl_i2c2_gpio: i2c2-gpio-grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
>;
};
pinctrl_lcdif: lcdif-grp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
>;
};
pinctrl_pwm1: pwm1-grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
>;
};
pinctrl_sai2: sai2-grp {
fsl,pins = <
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
>;
};
pinctrl_tsc: tsc-grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
>;
};
pinctrl_uart1: uart1-grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart6: uart6-grp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1
MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1
>;
};
pinctrl_usbotg1: usbotg1-grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usbotg2: usbotg2-grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x120b0
>;
};
pinctrl_usdhc2: usdhc2-grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 /* SD2 Reset */
>;
};
};
&iomuxc_snvs {
/* DHCOM GPIOs A..H */
pinctrl_snvs_dhcom_a: snvs-dhcom-a-grp {
fsl,pins = <MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x400120b0>;
};
pinctrl_snvs_dhcom_b: snvs-dhcom-b-grp {
fsl,pins = <MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x400120b0>;
};
pinctrl_snvs_dhcom_c: snvs-dhcom-c-grp {
fsl,pins = <MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x400120b0>;
};
pinctrl_snvs_dhcom_d: snvs-dhcom-d-grp {
fsl,pins = <MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x400120b0>;
};
pinctrl_snvs_dhcom_e: snvs-dhcom-e-grp {
fsl,pins = <MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x400120b0>;
};
pinctrl_snvs_dhcom_f: snvs-dhcom-f-grp {
fsl,pins = <MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x400120b0>;
};
pinctrl_snvs_dhcom_g: snvs-dhcom-g-grp {
fsl,pins = <MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x400120b0>;
};
pinctrl_snvs_dhcom_h: snvs-dhcom-h-grp {
fsl,pins = <MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400120b0>;
};
pinctrl_snvs_fec1_phy: snvs-fec1-phy-grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0xb1 /* SMSC PHY Int */
>;
};
pinctrl_snvs_fec2_phy: snvs-fec2-phy-grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0xb1 /* SMSC PHY Int */
>;
};
};
|
