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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright (C) 2020 SiFive, Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive Platform-Level Interrupt Controller (PLIC)
description:
SiFive SoCs and other RISC-V SoCs include an implementation of the
Platform-Level Interrupt Controller (PLIC) high-level specification in
the RISC-V Privileged Architecture specification. The PLIC connects all
external interrupts in the system to all hart contexts in the system, via
the external interrupt source in each hart.
A hart context is a privilege mode in a hardware execution thread. For example,
in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
privilege modes per hart; machine mode and supervisor mode.
Each interrupt can be enabled on per-context basis. Any context can claim
a pending enabled interrupt and then release it once it has been handled.
Each interrupt has a configurable priority. Higher priority interrupts are
serviced first. Each context can specify a priority threshold. Interrupts
with priority below this threshold will not cause the PLIC to raise its
interrupt line leading to the context.
While the PLIC supports both edge-triggered and level-triggered interrupts,
interrupt handlers are oblivious to this distinction and therefore it is not
specified in the PLIC device-tree binding.
While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
"sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
contains a specific memory layout, which is documented in chapter 8 of the
SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
maintainers:
- Sagar Kadam <sagar.kadam@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
- Palmer Dabbelt <palmer@dabbelt.com>
properties:
compatible:
items:
- enum:
- sifive,fu540-c000-plic
- canaan,k210-plic
- const: sifive,plic-1.0.0
reg:
maxItems: 1
'#address-cells':
const: 0
'#interrupt-cells':
const: 1
interrupt-controller: true
interrupts-extended:
minItems: 1
description:
Specifies which contexts are connected to the PLIC, with "-1" specifying
that a context is not present. Each node pointed to should be a
riscv,cpu-intc node, which has a riscv node as parent.
riscv,ndev:
$ref: "/schemas/types.yaml#/definitions/uint32"
description:
Specifies how many external interrupts are supported by this controller.
required:
- compatible
- '#address-cells'
- '#interrupt-cells'
- interrupt-controller
- reg
- interrupts-extended
- riscv,ndev
additionalProperties: false
examples:
- |
plic: interrupt-controller@c000000 {
#address-cells = <0>;
#interrupt-cells = <1>;
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
interrupt-controller;
interrupts-extended = <
&cpu0_intc 11
&cpu1_intc 11 &cpu1_intc 9
&cpu2_intc 11 &cpu2_intc 9
&cpu3_intc 11 &cpu3_intc 9
&cpu4_intc 11 &cpu4_intc 9>;
reg = <0xc000000 0x4000000>;
riscv,ndev = <10>;
};
|
