From 2a29f9d6fea82485941449c2328af5b2a4ea636f Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 27 Jul 2016 23:59:59 +0300 Subject: ARM: dts: r8a7794: add MSTP5 clocks Add some MSTP5 clocks to the R8A7794 device tree. Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- include/dt-bindings/clock/r8a7794-clock.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index a3491ba2f6ec..f8279eca033e 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -67,6 +67,7 @@ #define R8A7794_CLK_IRQC 7 /* MSTP5 */ +#define R8A7794_CLK_AUDIO_DMAC0 2 #define R8A7794_CLK_PWM 23 /* MSTP7 */ -- cgit v1.2.3-58-ga151 From 975fb77f874be95e50e653e90bcbcf09c08e66c2 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 27 Jul 2016 14:01:01 -0700 Subject: ARM: dts: r8a7794: add MSTP10 clocks Add MSTP10 clocks to the R8A7794 device tree. This patch is based on the commit ee9141522dcf ("ARM: shmobile: r8a7791: add MSTP10 support on DTSI"). Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 52 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/r8a7794-clock.h | 24 ++++++++++++++ 2 files changed, 76 insertions(+) (limited to 'include') diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 1c2d3846d70e..cba41c199fd8 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -1267,6 +1267,58 @@ "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; }; + mstp10_clks: mstp10_clks@e6150998 { + compatible = "renesas,r8a7794-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; + clocks = <&p_clk>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&p_clk>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7", + "ssi6", "ssi5", "ssi4", "ssi3", + "ssi2", "ssi1", "ssi0", + "scu-all", "scu-dvc1", "scu-dvc0", + "scu-ctu1-mix1", "scu-ctu0-mix0", + "scu-src6", "scu-src5", "scu-src4", + "scu-src3", "scu-src2", "scu-src1"; + }; mstp11_clks: mstp11_clks@e615099c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index f8279eca033e..9d02f5317c7c 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -108,6 +108,30 @@ #define R8A7794_CLK_I2C1 30 #define R8A7794_CLK_I2C0 31 +/* MSTP10 */ +#define R8A7794_CLK_SSI_ALL 5 +#define R8A7794_CLK_SSI9 6 +#define R8A7794_CLK_SSI8 7 +#define R8A7794_CLK_SSI7 8 +#define R8A7794_CLK_SSI6 9 +#define R8A7794_CLK_SSI5 10 +#define R8A7794_CLK_SSI4 11 +#define R8A7794_CLK_SSI3 12 +#define R8A7794_CLK_SSI2 13 +#define R8A7794_CLK_SSI1 14 +#define R8A7794_CLK_SSI0 15 +#define R8A7794_CLK_SCU_ALL 17 +#define R8A7794_CLK_SCU_DVC1 18 +#define R8A7794_CLK_SCU_DVC0 19 +#define R8A7794_CLK_SCU_CTU1_MIX1 20 +#define R8A7794_CLK_SCU_CTU0_MIX0 21 +#define R8A7794_CLK_SCU_SRC6 25 +#define R8A7794_CLK_SCU_SRC5 26 +#define R8A7794_CLK_SCU_SRC4 27 +#define R8A7794_CLK_SCU_SRC3 28 +#define R8A7794_CLK_SCU_SRC2 29 +#define R8A7794_CLK_SCU_SRC1 30 + /* MSTP11 */ #define R8A7794_CLK_SCIFA3 6 #define R8A7794_CLK_SCIFA4 7 -- cgit v1.2.3-58-ga151 From 18a21e2c079a01805607bb474b3536a99620d162 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Wed, 6 Jul 2016 21:28:34 +0800 Subject: soc: rockchip: add reboot-mode header Rockchip platform use a SYSCON mapped register store the reboot mode magic value for bootloader to use when system reboot. Add the shared header describing the values firmware expects for different boot modes. Signed-off-by: Andy Yan Reviewed-by: Matthias Brugger Signed-off-by: Heiko Stuebner --- include/dt-bindings/soc/rockchip,boot-mode.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 include/dt-bindings/soc/rockchip,boot-mode.h (limited to 'include') diff --git a/include/dt-bindings/soc/rockchip,boot-mode.h b/include/dt-bindings/soc/rockchip,boot-mode.h new file mode 100644 index 000000000000..ae7c867e736a --- /dev/null +++ b/include/dt-bindings/soc/rockchip,boot-mode.h @@ -0,0 +1,15 @@ +#ifndef __ROCKCHIP_BOOT_MODE_H +#define __ROCKCHIP_BOOT_MODE_H + +/*high 24 bits is tag, low 8 bits is type*/ +#define REBOOT_FLAG 0x5242C300 +/* normal boot */ +#define BOOT_NORMAL (REBOOT_FLAG + 0) +/* enter bootloader rockusb mode */ +#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1) +/* enter recovery */ +#define BOOT_RECOVERY (REBOOT_FLAG + 3) + /* enter fastboot mode */ +#define BOOT_FASTBOOT (REBOOT_FLAG + 9) + +#endif -- cgit v1.2.3-58-ga151 From 969244f9c72057b2c32b650b2d75a04d612c603c Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Thu, 1 Sep 2016 21:40:10 -0400 Subject: ARM: dts: r7s72100: add ethernet clock to device tree Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 9 +++++++++ include/dt-bindings/clock/r7s72100-clock.h | 3 +++ 2 files changed, 12 insertions(+) (limited to 'include') diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index e8e2a5d71976..6d29e8ffa0d9 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -108,6 +108,15 @@ clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; }; + mstp7_clks: mstp7_clks@fcfe0430 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0430 4>; + clocks = <&p0_clk>; + clock-indices = ; + clock-output-names = "ether"; + }; + mstp9_clks: mstp9_clks@fcfe0438 { #clock-cells = <1>; compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h index 5128f4d94f44..3cd813896d08 100644 --- a/include/dt-bindings/clock/r7s72100-clock.h +++ b/include/dt-bindings/clock/r7s72100-clock.h @@ -25,6 +25,9 @@ #define R7S72100_CLK_SCIF6 1 #define R7S72100_CLK_SCIF7 0 +/* MSTP7 */ +#define R7S72100_CLK_ETHER 4 + /* MSTP9 */ #define R7S72100_CLK_I2C0 7 #define R7S72100_CLK_I2C1 6 -- cgit v1.2.3-58-ga151 From 5db7e3bb87df9fc2a6d6cbc3384ff073070c8d1b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:04 +0200 Subject: pinctrl: dt-bindings: samsung: Add header with values used for configuration Hard-coded pinctrl configuration values are scattered through DTS files. The numbers are difficult to decode by human, especially without the datasheet. Additionally the drive strength differs between S3C64xx, S5PV210 and Exynos SoC families increasing the confusion. The header will help making this more readable and maintainable. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Linus Walleij --- MAINTAINERS | 2 ++ include/dt-bindings/pinctrl/samsung.h | 57 +++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100644 include/dt-bindings/pinctrl/samsung.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 20bb1d00098c..f5755866b960 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9236,6 +9236,8 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers) S: Maintained F: drivers/pinctrl/samsung/ +F: include/dt-bindings/pinctrl/samsung.h +F: Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt PIN CONTROLLER - SINGLE M: Tony Lindgren diff --git a/include/dt-bindings/pinctrl/samsung.h b/include/dt-bindings/pinctrl/samsung.h new file mode 100644 index 000000000000..6276eb785e2b --- /dev/null +++ b/include/dt-bindings/pinctrl/samsung.h @@ -0,0 +1,57 @@ +/* + * Samsung's Exynos pinctrl bindings + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Author: Krzysztof Kozlowski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__ +#define __DT_BINDINGS_PINCTRL_SAMSUNG_H__ + +#define EXYNOS_PIN_PULL_NONE 0 +#define EXYNOS_PIN_PULL_DOWN 1 +#define EXYNOS_PIN_PULL_UP 3 + +#define S3C64XX_PIN_PULL_NONE 0 +#define S3C64XX_PIN_PULL_DOWN 1 +#define S3C64XX_PIN_PULL_UP 2 + +/* Pin function in power down mode */ +#define EXYNOS_PIN_PDN_OUT0 0 +#define EXYNOS_PIN_PDN_OUT1 1 +#define EXYNOS_PIN_PDN_INPUT 2 +#define EXYNOS_PIN_PDN_PREV 3 + +/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ +#define EXYNOS4_PIN_DRV_LV1 0 +#define EXYNOS4_PIN_DRV_LV2 2 +#define EXYNOS4_PIN_DRV_LV3 1 +#define EXYNOS4_PIN_DRV_LV4 3 + +/* Drive strengths for Exynos5260 */ +#define EXYNOS5260_PIN_DRV_LV1 0 +#define EXYNOS5260_PIN_DRV_LV2 1 +#define EXYNOS5260_PIN_DRV_LV4 2 +#define EXYNOS5260_PIN_DRV_LV6 3 + +/* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */ +#define EXYNOS5420_PIN_DRV_LV1 0 +#define EXYNOS5420_PIN_DRV_LV2 1 +#define EXYNOS5420_PIN_DRV_LV3 2 +#define EXYNOS5420_PIN_DRV_LV4 3 + +#define EXYNOS_PIN_FUNC_INPUT 0 +#define EXYNOS_PIN_FUNC_OUTPUT 1 +#define EXYNOS_PIN_FUNC_2 2 +#define EXYNOS_PIN_FUNC_3 3 +#define EXYNOS_PIN_FUNC_4 4 +#define EXYNOS_PIN_FUNC_5 5 +#define EXYNOS_PIN_FUNC_6 6 +#define EXYNOS_PIN_FUNC_F 0xf + +#endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */ -- cgit v1.2.3-58-ga151